gwj / at91sam9263 · Commits

Commit 6958549d4f9ff6016784ff09d5898e084a15c59c

Authored by aurel32
1 parent 72d239ed

target-mips: fix indentation 

Remove all tabs from target-mips/*

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6306 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 4 changed files with 98 additions and 98 deletions
target-mips/helper.c
  View file @6958549
... ... @@ -134,18 +134,18 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
134 134 #if defined(TARGET_MIPS64)
135 135 } else if (address < 0x4000000000000000ULL) {
136 136 /* xuseg */
137   - if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
  137 + if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
138 138 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
139   - } else {
140   - ret = TLBRET_BADADDR;
  139 + } else {
  140 + ret = TLBRET_BADADDR;
141 141 }
142 142 } else if (address < 0x8000000000000000ULL) {
143 143 /* xsseg */
144   - if ((supervisor_mode || kernel_mode) &&
145   - SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
  144 + if ((supervisor_mode || kernel_mode) &&
  145 + SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
146 146 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
147   - } else {
148   - ret = TLBRET_BADADDR;
  147 + } else {
  148 + ret = TLBRET_BADADDR;
149 149 }
150 150 } else if (address < 0xC000000000000000ULL) {
151 151 /* xkphys */
... ... @@ -153,17 +153,17 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
153 153 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
154 154 *physical = address & env->PAMask;
155 155 *prot = PAGE_READ | PAGE_WRITE;
156   - } else {
157   - ret = TLBRET_BADADDR;
158   - }
  156 + } else {
  157 + ret = TLBRET_BADADDR;
  158 + }
159 159 } else if (address < 0xFFFFFFFF80000000ULL) {
160 160 /* xkseg */
161   - if (kernel_mode && KX &&
162   - address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
  161 + if (kernel_mode && KX &&
  162 + address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
163 163 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
164   - } else {
165   - ret = TLBRET_BADADDR;
166   - }
  164 + } else {
  165 + ret = TLBRET_BADADDR;
  166 + }
167 167 #endif
168 168 } else if (address < (int32_t)0xA0000000UL) {
169 169 /* kseg0 */
... ... @@ -200,7 +200,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
200 200 #if 0
201 201 if (logfile) {
202 202 fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
203   - address, rw, access_type, *physical, *prot, ret);
  203 + address, rw, access_type, *physical, *prot, ret);
204 204 }
205 205 #endif
206 206  
... ... @@ -297,7 +297,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
297 297 /* Raise exception */
298 298 env->CP0_BadVAddr = address;
299 299 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
300   - ((address >> 9) & 0x007ffff0);
  300 + ((address >> 9) & 0x007ffff0);
301 301 env->CP0_EntryHi =
302 302 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
303 303 #if defined(TARGET_MIPS64)
... ... @@ -593,8 +593,8 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
593 593  
594 594 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
595 595 /* For tlbwr, we can shadow the discarded entry into
596   - a new (fake) TLB entry, as long as the guest can not
597   - tell that it's there. */
  596 + a new (fake) TLB entry, as long as the guest can not
  597 + tell that it's there. */
598 598 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
599 599 env->tlb->tlb_in_use++;
600 600 return;
... ...
target-mips/op_helper.c
  View file @6958549
... ... @@ -1518,7 +1518,7 @@ target_ulong do_yield(target_ulong t0)
1518 1518 }
1519 1519 }
1520 1520 } else if (t0 == 0) {
1521   - if (0 /* TODO: TC underflow */) {
  1521 + if (0 /* TODO: TC underflow */) {
1522 1522 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1523 1523 do_raise_exception(EXCP_THREAD);
1524 1524 } else {
... ... @@ -1622,17 +1622,17 @@ void r4k_do_tlbp (void)
1622 1622 if (i == env->tlb->nb_tlb) {
1623 1623 /* No match. Discard any shadow entries, if any of them match. */
1624 1624 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1625   - tlb = &env->tlb->mmu.r4k.tlb[i];
1626   - /* 1k pages are not supported. */
1627   - mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1628   - tag = env->CP0_EntryHi & ~mask;
1629   - VPN = tlb->VPN & ~mask;
1630   - /* Check ASID, virtual page number & size */
1631   - if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  1625 + tlb = &env->tlb->mmu.r4k.tlb[i];
  1626 + /* 1k pages are not supported. */
  1627 + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  1628 + tag = env->CP0_EntryHi & ~mask;
  1629 + VPN = tlb->VPN & ~mask;
  1630 + /* Check ASID, virtual page number & size */
  1631 + if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1632 1632 r4k_mips_tlb_flush_extra (env, i);
1633   - break;
1634   - }
1635   - }
  1633 + break;
  1634 + }
  1635 + }
1636 1636  
1637 1637 env->CP0_Index |= 0x80000000;
1638 1638 }
... ...
target-mips/translate.c
  View file @6958549
... ... @@ -1092,7 +1092,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1092 1092 break;
1093 1093 case OPC_LWL:
1094 1094 save_cpu_state(ctx, 1);
1095   - gen_load_gpr(t1, rt);
  1095 + gen_load_gpr(t1, rt);
1096 1096 gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
1097 1097 gen_store_gpr(t1, rt);
1098 1098 opn = "lwl";
... ... @@ -1105,7 +1105,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1105 1105 break;
1106 1106 case OPC_LWR:
1107 1107 save_cpu_state(ctx, 1);
1108   - gen_load_gpr(t1, rt);
  1108 + gen_load_gpr(t1, rt);
1109 1109 gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
1110 1110 gen_store_gpr(t1, rt);
1111 1111 opn = "lwr";
... ... @@ -2076,59 +2076,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2076 2076 case OPC_VR54XX_MULS:
2077 2077 gen_helper_muls(t0, t0, t1);
2078 2078 opn = "muls";
2079   - break;
  2079 + break;
2080 2080 case OPC_VR54XX_MULSU:
2081 2081 gen_helper_mulsu(t0, t0, t1);
2082 2082 opn = "mulsu";
2083   - break;
  2083 + break;
2084 2084 case OPC_VR54XX_MACC:
2085 2085 gen_helper_macc(t0, t0, t1);
2086 2086 opn = "macc";
2087   - break;
  2087 + break;
2088 2088 case OPC_VR54XX_MACCU:
2089 2089 gen_helper_maccu(t0, t0, t1);
2090 2090 opn = "maccu";
2091   - break;
  2091 + break;
2092 2092 case OPC_VR54XX_MSAC:
2093 2093 gen_helper_msac(t0, t0, t1);
2094 2094 opn = "msac";
2095   - break;
  2095 + break;
2096 2096 case OPC_VR54XX_MSACU:
2097 2097 gen_helper_msacu(t0, t0, t1);
2098 2098 opn = "msacu";
2099   - break;
  2099 + break;
2100 2100 case OPC_VR54XX_MULHI:
2101 2101 gen_helper_mulhi(t0, t0, t1);
2102 2102 opn = "mulhi";
2103   - break;
  2103 + break;
2104 2104 case OPC_VR54XX_MULHIU:
2105 2105 gen_helper_mulhiu(t0, t0, t1);
2106 2106 opn = "mulhiu";
2107   - break;
  2107 + break;
2108 2108 case OPC_VR54XX_MULSHI:
2109 2109 gen_helper_mulshi(t0, t0, t1);
2110 2110 opn = "mulshi";
2111   - break;
  2111 + break;
2112 2112 case OPC_VR54XX_MULSHIU:
2113 2113 gen_helper_mulshiu(t0, t0, t1);
2114 2114 opn = "mulshiu";
2115   - break;
  2115 + break;
2116 2116 case OPC_VR54XX_MACCHI:
2117 2117 gen_helper_macchi(t0, t0, t1);
2118 2118 opn = "macchi";
2119   - break;
  2119 + break;
2120 2120 case OPC_VR54XX_MACCHIU:
2121 2121 gen_helper_macchiu(t0, t0, t1);
2122 2122 opn = "macchiu";
2123   - break;
  2123 + break;
2124 2124 case OPC_VR54XX_MSACHI:
2125 2125 gen_helper_msachi(t0, t0, t1);
2126 2126 opn = "msachi";
2127   - break;
  2127 + break;
2128 2128 case OPC_VR54XX_MSACHIU:
2129 2129 gen_helper_msachiu(t0, t0, t1);
2130 2130 opn = "msachiu";
2131   - break;
  2131 + break;
2132 2132 default:
2133 2133 MIPS_INVAL("mul vr54xx");
2134 2134 generate_exception(ctx, EXCP_RI);
... ... @@ -2323,7 +2323,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2323 2323 fprintf(logfile,
2324 2324 "Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
2325 2325 ctx->pc);
2326   - }
  2326 + }
2327 2327 #endif
2328 2328 generate_exception(ctx, EXCP_RI);
2329 2329 goto out;
... ... @@ -5763,7 +5763,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5763 5763 gen_load_fpr32(fp0, fs);
5764 5764 tcg_gen_ext_i32_tl(t0, fp0);
5765 5765 tcg_temp_free_i32(fp0);
5766   - }
  5766 + }
5767 5767 gen_store_gpr(t0, rt);
5768 5768 opn = "mfc1";
5769 5769 break;
... ... @@ -5775,7 +5775,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5775 5775 tcg_gen_trunc_tl_i32(fp0, t0);
5776 5776 gen_store_fpr32(fp0, fs);
5777 5777 tcg_temp_free_i32(fp0);
5778   - }
  5778 + }
5779 5779 opn = "mtc1";
5780 5780 break;
5781 5781 case OPC_CFC1:
... ... @@ -5795,7 +5795,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5795 5795 gen_load_fpr64(ctx, fp0, fs);
5796 5796 tcg_gen_trunc_i64_tl(t0, fp0);
5797 5797 tcg_temp_free_i64(fp0);
5798   - }
  5798 + }
5799 5799 gen_store_gpr(t0, rt);
5800 5800 opn = "dmfc1";
5801 5801 break;
... ... @@ -5807,7 +5807,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5807 5807 tcg_gen_extu_tl_i64(fp0, t0);
5808 5808 gen_store_fpr64(ctx, fp0, fs);
5809 5809 tcg_temp_free_i64(fp0);
5810   - }
  5810 + }
5811 5811 opn = "dmtc1";
5812 5812 break;
5813 5813 case OPC_MFHC1:
... ... @@ -5817,7 +5817,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5817 5817 gen_load_fpr32h(fp0, fs);
5818 5818 tcg_gen_ext_i32_tl(t0, fp0);
5819 5819 tcg_temp_free_i32(fp0);
5820   - }
  5820 + }
5821 5821 gen_store_gpr(t0, rt);
5822 5822 opn = "mfhc1";
5823 5823 break;
... ... @@ -5829,7 +5829,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5829 5829 tcg_gen_trunc_tl_i32(fp0, t0);
5830 5830 gen_store_fpr32h(fp0, fs);
5831 5831 tcg_temp_free_i32(fp0);
5832   - }
  5832 + }
5833 5833 opn = "mthc1";
5834 5834 break;
5835 5835 default:
... ... @@ -8339,7 +8339,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
8339 8339 save_cpu_state(&ctx, ctx.bstate == BS_NONE);
8340 8340 gen_helper_0i(raise_exception, EXCP_DEBUG);
8341 8341 } else {
8342   - switch (ctx.bstate) {
  8342 + switch (ctx.bstate) {
8343 8343 case BS_STOP:
8344 8344 gen_helper_interrupt_restart();
8345 8345 gen_goto_tb(&ctx, 0, ctx.pc);
... ... @@ -8355,7 +8355,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
8355 8355 case BS_BRANCH:
8356 8356 default:
8357 8357 break;
8358   - }
  8358 + }
8359 8359 }
8360 8360 done_generating:
8361 8361 gen_icount_end(tb, num_insns);
... ... @@ -8499,7 +8499,7 @@ static void mips_tcg_init(void)
8499 8499  
8500 8500 /* Initialize various static tables. */
8501 8501 if (inited)
8502   - return;
  8502 + return;
8503 8503  
8504 8504 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8505 8505 for (i = 0; i < 32; i++)
... ...
target-mips/translate_init.c
  View file @6958549
... ... @@ -102,8 +102,8 @@ static const mips_def_t mips_defs[] =
102 102 .CP0_PRid = 0x00018000,
103 103 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
104 104 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
105   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
106   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  105 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  106 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
107 107 .CP0_Config2 = MIPS_CONFIG2,
108 108 .CP0_Config3 = MIPS_CONFIG3,
109 109 .SYNCI_Step = 32,
... ... @@ -121,8 +121,8 @@ static const mips_def_t mips_defs[] =
121 121 no virtual icache, uncached coherency. */
122 122 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
123 123 .CP0_Config1 = MIPS_CONFIG1 |
124   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
125   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  124 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  125 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
126 126 .CP0_Config2 = MIPS_CONFIG2,
127 127 .CP0_Config3 = MIPS_CONFIG3,
128 128 .SYNCI_Step = 32,
... ... @@ -138,8 +138,8 @@ static const mips_def_t mips_defs[] =
138 138 .CP0_PRid = 0x00018400,
139 139 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
140 140 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
141   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
142   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  141 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  142 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
143 143 .CP0_Config2 = MIPS_CONFIG2,
144 144 .CP0_Config3 = MIPS_CONFIG3,
145 145 .SYNCI_Step = 32,
... ... @@ -155,8 +155,8 @@ static const mips_def_t mips_defs[] =
155 155 .CP0_PRid = 0x00018500,
156 156 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
157 157 .CP0_Config1 = MIPS_CONFIG1 |
158   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
159   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  158 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  159 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
160 160 .CP0_Config2 = MIPS_CONFIG2,
161 161 .CP0_Config3 = MIPS_CONFIG3,
162 162 .SYNCI_Step = 32,
... ... @@ -173,8 +173,8 @@ static const mips_def_t mips_defs[] =
173 173 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
174 174 (MMU_TYPE_R4000 << CP0C0_MT),
175 175 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
176   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
177   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  176 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  177 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
178 178 .CP0_Config2 = MIPS_CONFIG2,
179 179 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
180 180 .SYNCI_Step = 32,
... ... @@ -189,10 +189,10 @@ static const mips_def_t mips_defs[] =
189 189 .name = "4KEm",
190 190 .CP0_PRid = 0x00019100,
191 191 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
192   - (MMU_TYPE_FMT << CP0C0_MT),
  192 + (MMU_TYPE_FMT << CP0C0_MT),
193 193 .CP0_Config1 = MIPS_CONFIG1 |
194   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
195   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  194 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  195 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
196 196 .CP0_Config2 = MIPS_CONFIG2,
197 197 .CP0_Config3 = MIPS_CONFIG3,
198 198 .SYNCI_Step = 32,
... ... @@ -207,10 +207,10 @@ static const mips_def_t mips_defs[] =
207 207 .name = "24Kc",
208 208 .CP0_PRid = 0x00019300,
209 209 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
210   - (MMU_TYPE_R4000 << CP0C0_MT),
  210 + (MMU_TYPE_R4000 << CP0C0_MT),
211 211 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
212   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
213   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  212 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  213 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
214 214 .CP0_Config2 = MIPS_CONFIG2,
215 215 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
216 216 .SYNCI_Step = 32,
... ... @@ -228,8 +228,8 @@ static const mips_def_t mips_defs[] =
228 228 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
229 229 (MMU_TYPE_R4000 << CP0C0_MT),
230 230 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
231   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
232   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  231 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  232 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
233 233 .CP0_Config2 = MIPS_CONFIG2,
234 234 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
235 235 .SYNCI_Step = 32,
... ... @@ -247,10 +247,10 @@ static const mips_def_t mips_defs[] =
247 247 .name = "34Kf",
248 248 .CP0_PRid = 0x00019500,
249 249 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
250   - (MMU_TYPE_R4000 << CP0C0_MT),
  250 + (MMU_TYPE_R4000 << CP0C0_MT),
251 251 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
252   - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
253   - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  252 + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  253 + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
254 254 .CP0_Config2 = MIPS_CONFIG2,
255 255 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
256 256 .SYNCI_Step = 32,
... ... @@ -293,12 +293,12 @@ static const mips_def_t mips_defs[] =
293 293 .CP0_PRid = 0x00000400,
294 294 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
295 295 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
296   - /* Note: Config1 is only used internally, the R4000 has only Config0. */
  296 + /* Note: Config1 is only used internally, the R4000 has only Config0. */
297 297 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
298 298 .SYNCI_Step = 16,
299 299 .CCRes = 2,
300 300 .CP0_Status_rw_bitmask = 0x3678FFFF,
301   - /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
  301 + /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
302 302 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
303 303 .SEGBITS = 40,
304 304 .PABITS = 36,
... ... @@ -325,11 +325,11 @@ static const mips_def_t mips_defs[] =
325 325 .name = "5Kc",
326 326 .CP0_PRid = 0x00018100,
327 327 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
328   - (MMU_TYPE_R4000 << CP0C0_MT),
  328 + (MMU_TYPE_R4000 << CP0C0_MT),
329 329 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
330   - (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
331   - (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
332   - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
  330 + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
  331 + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
  332 + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
333 333 .CP0_Config2 = MIPS_CONFIG2,
334 334 .CP0_Config3 = MIPS_CONFIG3,
335 335 .SYNCI_Step = 32,
... ... @@ -344,17 +344,17 @@ static const mips_def_t mips_defs[] =
344 344 .name = "5Kf",
345 345 .CP0_PRid = 0x00018100,
346 346 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
347   - (MMU_TYPE_R4000 << CP0C0_MT),
  347 + (MMU_TYPE_R4000 << CP0C0_MT),
348 348 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
349   - (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
350   - (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
351   - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
  349 + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
  350 + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
  351 + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
352 352 .CP0_Config2 = MIPS_CONFIG2,
353 353 .CP0_Config3 = MIPS_CONFIG3,
354 354 .SYNCI_Step = 32,
355 355 .CCRes = 2,
356 356 .CP0_Status_rw_bitmask = 0x36F8FFFF,
357   - /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
  357 + /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
358 358 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
359 359 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
360 360 .SEGBITS = 42,
... ... @@ -364,21 +364,21 @@ static const mips_def_t mips_defs[] =
364 364 },
365 365 {
366 366 .name = "20Kc",
367   - /* We emulate a later version of the 20Kc, earlier ones had a broken
  367 + /* We emulate a later version of the 20Kc, earlier ones had a broken
368 368 WAIT instruction. */
369 369 .CP0_PRid = 0x000182a0,
370 370 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
371 371 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
372 372 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
373   - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
374   - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
375   - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
  373 + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
  374 + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
  375 + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
376 376 .CP0_Config2 = MIPS_CONFIG2,
377 377 .CP0_Config3 = MIPS_CONFIG3,
378 378 .SYNCI_Step = 32,
379 379 .CCRes = 1,
380 380 .CP0_Status_rw_bitmask = 0x36FBFFFF,
381   - /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
  381 + /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
382 382 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
383 383 (1 << FCR0_D) | (1 << FCR0_S) |
384 384 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
... ... @@ -388,16 +388,16 @@ static const mips_def_t mips_defs[] =
388 388 .mmu_type = MMU_TYPE_R4000,
389 389 },
390 390 {
391   - /* A generic CPU providing MIPS64 Release 2 features.
  391 + /* A generic CPU providing MIPS64 Release 2 features.
392 392 FIXME: Eventually this should be replaced by a real CPU model. */
393 393 .name = "MIPS64R2-generic",
394 394 .CP0_PRid = 0x00010000,
395 395 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
396   - (MMU_TYPE_R4000 << CP0C0_MT),
  396 + (MMU_TYPE_R4000 << CP0C0_MT),
397 397 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
398   - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
399   - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
400   - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
  398 + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
  399 + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
  400 + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
401 401 .CP0_Config2 = MIPS_CONFIG2,
402 402 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
403 403 .SYNCI_Step = 32,
... ...