Commit 69135b5c04541a8f130a374ae2c063eeeca873e3
1 parent
69b91039
suppressed pci2isa.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@819 c046a42c-6fe2-441c-8c8c-71466251a162
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108 deletions
Makefile.target
| ... | ... | @@ -232,7 +232,7 @@ ifeq ($(ARCH),alpha) |
| 232 | 232 | endif |
| 233 | 233 | |
| 234 | 234 | # must use static linking to avoid leaving stuff in virtual address space |
| 235 | -VL_OBJS=vl.o osdep.o block.o monitor.o pci.o pci2isa.o | |
| 235 | +VL_OBJS=vl.o osdep.o block.o monitor.o pci.o | |
| 236 | 236 | |
| 237 | 237 | ifeq ($(TARGET_ARCH), i386) |
| 238 | 238 | # Hardware support | ... | ... |
hw/pci2isa.c deleted
100644 → 0
| 1 | -/* | |
| 2 | - * QEMU PCI to ISA bridge | |
| 3 | - * | |
| 4 | - * Copyright (c) 2004 Fabrice Bellard | |
| 5 | - * | |
| 6 | - * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 7 | - * of this software and associated documentation files (the "Software"), to deal | |
| 8 | - * in the Software without restriction, including without limitation the rights | |
| 9 | - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 10 | - * copies of the Software, and to permit persons to whom the Software is | |
| 11 | - * furnished to do so, subject to the following conditions: | |
| 12 | - * | |
| 13 | - * The above copyright notice and this permission notice shall be included in | |
| 14 | - * all copies or substantial portions of the Software. | |
| 15 | - * | |
| 16 | - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 20 | - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 21 | - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 22 | - * THE SOFTWARE. | |
| 23 | - */ | |
| 24 | -#include "vl.h" | |
| 25 | - | |
| 26 | -//#define DEBUG_PCI | |
| 27 | - | |
| 28 | -typedef struct PIIX3State { | |
| 29 | - PCIDevice dev; | |
| 30 | - uint8_t elcr1; | |
| 31 | - uint8_t elcr2; | |
| 32 | -} PIIX3State; | |
| 33 | - | |
| 34 | -static void piix3_reset(PIIX3State *d) | |
| 35 | -{ | |
| 36 | - uint8_t *pci_conf = d->dev.config; | |
| 37 | - | |
| 38 | - pci_conf[0x04] = 0x07; // master, memory and I/O | |
| 39 | - pci_conf[0x05] = 0x00; | |
| 40 | - pci_conf[0x06] = 0x00; | |
| 41 | - pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
| 42 | - pci_conf[0x4c] = 0x4d; | |
| 43 | - pci_conf[0x4e] = 0x03; | |
| 44 | - pci_conf[0x4f] = 0x00; | |
| 45 | - pci_conf[0x60] = 0x80; | |
| 46 | - pci_conf[0x69] = 0x02; | |
| 47 | - pci_conf[0x70] = 0x80; | |
| 48 | - pci_conf[0x76] = 0x0c; | |
| 49 | - pci_conf[0x77] = 0x0c; | |
| 50 | - pci_conf[0x78] = 0x02; | |
| 51 | - pci_conf[0x79] = 0x00; | |
| 52 | - pci_conf[0x80] = 0x00; | |
| 53 | - pci_conf[0x82] = 0x00; | |
| 54 | - pci_conf[0xa0] = 0x08; | |
| 55 | - pci_conf[0xa0] = 0x08; | |
| 56 | - pci_conf[0xa2] = 0x00; | |
| 57 | - pci_conf[0xa3] = 0x00; | |
| 58 | - pci_conf[0xa4] = 0x00; | |
| 59 | - pci_conf[0xa5] = 0x00; | |
| 60 | - pci_conf[0xa6] = 0x00; | |
| 61 | - pci_conf[0xa7] = 0x00; | |
| 62 | - pci_conf[0xa8] = 0x0f; | |
| 63 | - pci_conf[0xaa] = 0x00; | |
| 64 | - pci_conf[0xab] = 0x00; | |
| 65 | - pci_conf[0xac] = 0x00; | |
| 66 | - pci_conf[0xae] = 0x00; | |
| 67 | - | |
| 68 | - d->elcr1 = 0x00; | |
| 69 | - d->elcr2 = 0x00; | |
| 70 | -} | |
| 71 | - | |
| 72 | -static uint32_t piix3_read_config(PCIDevice *d, | |
| 73 | - uint32_t address, int len) | |
| 74 | -{ | |
| 75 | - uint32_t val; | |
| 76 | - val = 0; | |
| 77 | - memcpy(&val, d->config + address, len); | |
| 78 | - return val; | |
| 79 | -} | |
| 80 | - | |
| 81 | -static void piix3_write_config(PCIDevice *d, | |
| 82 | - uint32_t address, uint32_t val, int len) | |
| 83 | -{ | |
| 84 | - memcpy(d->config + address, &val, len); | |
| 85 | -} | |
| 86 | - | |
| 87 | -void piix3_init(void) | |
| 88 | -{ | |
| 89 | - PIIX3State *d; | |
| 90 | - uint8_t *pci_conf; | |
| 91 | - | |
| 92 | - d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State), | |
| 93 | - 0, -1, | |
| 94 | - piix3_read_config, | |
| 95 | - piix3_write_config); | |
| 96 | - pci_conf = d->dev.config; | |
| 97 | - | |
| 98 | - pci_conf[0x00] = 0x86; // Intel | |
| 99 | - pci_conf[0x01] = 0x80; | |
| 100 | - pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) | |
| 101 | - pci_conf[0x03] = 0x70; | |
| 102 | - pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA | |
| 103 | - pci_conf[0x0b] = 0x06; // class_base = PCI_bridge | |
| 104 | - pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic | |
| 105 | - | |
| 106 | - piix3_reset(d); | |
| 107 | -} |