Commit 68db3767e6423e28fa55ff46e6863b5fff889770

Authored by Filip Navara
1 parent c280d62e

Convert disas_vfp_insn not to use cpu_T.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Showing 1 changed file with 21 additions and 28 deletions
target-arm/translate.c
@@ -180,12 +180,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var) @@ -180,12 +180,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
180 dead_tmp(var); 180 dead_tmp(var);
181 } 181 }
182 182
183 -  
184 -/* Basic operations. */  
185 -#define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im)  
186 -  
187 -#define gen_op_addl_T1_im(im) tcg_gen_addi_i32(cpu_T[1], cpu_T[1], im)  
188 -  
189 /* Value extensions. */ 183 /* Value extensions. */
190 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var) 184 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
191 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var) 185 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
@@ -824,11 +818,6 @@ static inline void gen_st32(TCGv val, TCGv addr, int index) @@ -824,11 +818,6 @@ static inline void gen_st32(TCGv val, TCGv addr, int index)
824 dead_tmp(val); 818 dead_tmp(val);
825 } 819 }
826 820
827 -static inline void gen_movl_T1_reg(DisasContext *s, int reg)  
828 -{  
829 - load_reg_var(s, cpu_T[1], reg);  
830 -}  
831 -  
832 static inline void gen_set_pc_im(uint32_t val) 821 static inline void gen_set_pc_im(uint32_t val)
833 { 822 {
834 tcg_gen_movi_i32(cpu_R[15], val); 823 tcg_gen_movi_i32(cpu_R[15], val);
@@ -1048,20 +1037,20 @@ VFP_GEN_FIX(uhto) @@ -1048,20 +1037,20 @@ VFP_GEN_FIX(uhto)
1048 VFP_GEN_FIX(ulto) 1037 VFP_GEN_FIX(ulto)
1049 #undef VFP_GEN_FIX 1038 #undef VFP_GEN_FIX
1050 1039
1051 -static inline void gen_vfp_ld(DisasContext *s, int dp) 1040 +static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
1052 { 1041 {
1053 if (dp) 1042 if (dp)
1054 - tcg_gen_qemu_ld64(cpu_F0d, cpu_T[1], IS_USER(s)); 1043 + tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
1055 else 1044 else
1056 - tcg_gen_qemu_ld32u(cpu_F0s, cpu_T[1], IS_USER(s)); 1045 + tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
1057 } 1046 }
1058 1047
1059 -static inline void gen_vfp_st(DisasContext *s, int dp) 1048 +static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
1060 { 1049 {
1061 if (dp) 1050 if (dp)
1062 - tcg_gen_qemu_st64(cpu_F0d, cpu_T[1], IS_USER(s)); 1051 + tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
1063 else 1052 else
1064 - tcg_gen_qemu_st32(cpu_F0s, cpu_T[1], IS_USER(s)); 1053 + tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
1065 } 1054 }
1066 1055
1067 static inline long 1056 static inline long
@@ -2617,6 +2606,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) @@ -2617,6 +2606,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2617 { 2606 {
2618 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; 2607 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2619 int dp, veclen; 2608 int dp, veclen;
  2609 + TCGv addr;
2620 TCGv tmp; 2610 TCGv tmp;
2621 TCGv tmp2; 2611 TCGv tmp2;
2622 2612
@@ -3207,22 +3197,23 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) @@ -3207,22 +3197,23 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
3207 else 3197 else
3208 rd = VFP_SREG_D(insn); 3198 rd = VFP_SREG_D(insn);
3209 if (s->thumb && rn == 15) { 3199 if (s->thumb && rn == 15) {
3210 - gen_op_movl_T1_im(s->pc & ~2); 3200 + addr = new_tmp();
  3201 + tcg_gen_movi_i32(addr, s->pc & ~2);
3211 } else { 3202 } else {
3212 - gen_movl_T1_reg(s, rn); 3203 + addr = load_reg(s, rn);
3213 } 3204 }
3214 if ((insn & 0x01200000) == 0x01000000) { 3205 if ((insn & 0x01200000) == 0x01000000) {
3215 /* Single load/store */ 3206 /* Single load/store */
3216 offset = (insn & 0xff) << 2; 3207 offset = (insn & 0xff) << 2;
3217 if ((insn & (1 << 23)) == 0) 3208 if ((insn & (1 << 23)) == 0)
3218 offset = -offset; 3209 offset = -offset;
3219 - gen_op_addl_T1_im(offset); 3210 + tcg_gen_addi_i32(addr, addr, offset);
3220 if (insn & (1 << 20)) { 3211 if (insn & (1 << 20)) {
3221 - gen_vfp_ld(s, dp); 3212 + gen_vfp_ld(s, dp, addr);
3222 gen_mov_vreg_F0(dp, rd); 3213 gen_mov_vreg_F0(dp, rd);
3223 } else { 3214 } else {
3224 gen_mov_F0_vreg(dp, rd); 3215 gen_mov_F0_vreg(dp, rd);
3225 - gen_vfp_st(s, dp); 3216 + gen_vfp_st(s, dp, addr);
3226 } 3217 }
3227 } else { 3218 } else {
3228 /* load/store multiple */ 3219 /* load/store multiple */
@@ -3232,7 +3223,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) @@ -3232,7 +3223,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
3232 n = insn & 0xff; 3223 n = insn & 0xff;
3233 3224
3234 if (insn & (1 << 24)) /* pre-decrement */ 3225 if (insn & (1 << 24)) /* pre-decrement */
3235 - gen_op_addl_T1_im(-((insn & 0xff) << 2)); 3226 + tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3236 3227
3237 if (dp) 3228 if (dp)
3238 offset = 8; 3229 offset = 8;
@@ -3241,14 +3232,14 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) @@ -3241,14 +3232,14 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
3241 for (i = 0; i < n; i++) { 3232 for (i = 0; i < n; i++) {
3242 if (insn & ARM_CP_RW_BIT) { 3233 if (insn & ARM_CP_RW_BIT) {
3243 /* load */ 3234 /* load */
3244 - gen_vfp_ld(s, dp); 3235 + gen_vfp_ld(s, dp, addr);
3245 gen_mov_vreg_F0(dp, rd + i); 3236 gen_mov_vreg_F0(dp, rd + i);
3246 } else { 3237 } else {
3247 /* store */ 3238 /* store */
3248 gen_mov_F0_vreg(dp, rd + i); 3239 gen_mov_F0_vreg(dp, rd + i);
3249 - gen_vfp_st(s, dp); 3240 + gen_vfp_st(s, dp, addr);
3250 } 3241 }
3251 - gen_op_addl_T1_im(offset); 3242 + tcg_gen_addi_i32(addr, addr, offset);
3252 } 3243 }
3253 if (insn & (1 << 21)) { 3244 if (insn & (1 << 21)) {
3254 /* writeback */ 3245 /* writeback */
@@ -3260,8 +3251,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) @@ -3260,8 +3251,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
3260 offset = 0; 3251 offset = 0;
3261 3252
3262 if (offset != 0) 3253 if (offset != 0)
3263 - gen_op_addl_T1_im(offset);  
3264 - gen_movl_reg_T1(s, rn); 3254 + tcg_gen_addi_i32(addr, addr, offset);
  3255 + store_reg(s, rn, addr);
  3256 + } else {
  3257 + dead_tmp(addr);
3265 } 3258 }
3266 } 3259 }
3267 } 3260 }