Commit 688890f75e399f3e96c5887d41958f6a7a65873c
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b4f8d821
target-ppc: Add SPE register read/write using XML
Don't read/write SPEFSCR until we figure out what to do about exceptions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
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target-ppc/translate_init.c
... | ... | @@ -9345,6 +9345,51 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n) |
9345 | 9345 | return 0; |
9346 | 9346 | } |
9347 | 9347 | |
9348 | +static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n) | |
9349 | +{ | |
9350 | + if (n < 32) { | |
9351 | +#if defined(TARGET_PPC64) | |
9352 | + stl_p(mem_buf, env->gpr[n] >> 32); | |
9353 | +#else | |
9354 | + stl_p(mem_buf, env->gprh[n]); | |
9355 | +#endif | |
9356 | + return 4; | |
9357 | + } | |
9358 | + if (n == 33) { | |
9359 | + stq_p(mem_buf, env->spe_acc); | |
9360 | + return 8; | |
9361 | + } | |
9362 | + if (n == 34) { | |
9363 | + /* SPEFSCR not implemented */ | |
9364 | + memset(mem_buf, 0, 4); | |
9365 | + return 4; | |
9366 | + } | |
9367 | + return 0; | |
9368 | +} | |
9369 | + | |
9370 | +static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n) | |
9371 | +{ | |
9372 | + if (n < 32) { | |
9373 | +#if defined(TARGET_PPC64) | |
9374 | + target_ulong lo = (uint32_t)env->gpr[n]; | |
9375 | + target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32; | |
9376 | + env->gpr[n] = lo | hi; | |
9377 | +#else | |
9378 | + env->gprh[n] = ldl_p(mem_buf); | |
9379 | +#endif | |
9380 | + return 4; | |
9381 | + } | |
9382 | + if (n == 33) { | |
9383 | + env->spe_acc = ldq_p(mem_buf); | |
9384 | + return 8; | |
9385 | + } | |
9386 | + if (n == 34) { | |
9387 | + /* SPEFSCR not implemented */ | |
9388 | + return 4; | |
9389 | + } | |
9390 | + return 0; | |
9391 | +} | |
9392 | + | |
9348 | 9393 | int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) |
9349 | 9394 | { |
9350 | 9395 | env->msr_mask = def->msr_mask; |
... | ... | @@ -9366,6 +9411,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) |
9366 | 9411 | gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg, |
9367 | 9412 | 34, "power-altivec.xml", 0); |
9368 | 9413 | } |
9414 | + if ((def->insns_flags & PPC_SPE) | (def->insns_flags & PPC_SPEFPU)) { | |
9415 | + gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg, | |
9416 | + 34, "power-spe.xml", 0); | |
9417 | + } | |
9418 | + | |
9369 | 9419 | #if defined(PPC_DUMP_CPU) |
9370 | 9420 | { |
9371 | 9421 | const char *mmu_model, *excp_model, *bus_model; | ... | ... |