gwj / at91sam9263 · Commits

Commit 67e999be93410b9eb7024d879d8e4cf6ce124eed

Authored by bellard
1 parent 91cc0295

Separate the DMA controllers - Convert ESP to new DMA methods (Blue Swirl) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2143 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 338 additions and 173 deletions
Makefile.target
  View file @67e999b
... ... @@ -359,8 +359,8 @@ VL_OBJS+= sun4u.o ide.o pckbd.o ps2.o vga.o apb_pci.o
359 359 VL_OBJS+= fdc.o mc146818rtc.o serial.o m48t59.o
360 360 VL_OBJS+= cirrus_vga.o parallel.o
361 361 else
362   -VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t59.o slavio_intctl.o
363   -VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o
  362 +VL_OBJS+= sun4m.o tcx.o pcnet.o iommu.o m48t59.o slavio_intctl.o
  363 +VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o sparc32_dma.o
364 364 endif
365 365 endif
366 366 ifeq ($(TARGET_BASE_ARCH), arm)
... ...
hw/esp.c
  View file @67e999b
1 1 /*
2   - * QEMU ESP emulation
  2 + * QEMU ESP/NCR53C9x emulation
3 3 *
4 4 * Copyright (c) 2005-2006 Fabrice Bellard
5 5 *
... ... @@ -26,33 +26,31 @@
26 26 /* debug ESP card */
27 27 //#define DEBUG_ESP
28 28  
  29 +/*
  30 + * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
  31 + * produced as NCR89C100. See
  32 + * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  33 + * and
  34 + * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  35 + */
  36 +
29 37 #ifdef DEBUG_ESP
30 38 #define DPRINTF(fmt, args...) \
31 39 do { printf("ESP: " fmt , ##args); } while (0)
32   -#define pic_set_irq(irq, level) \
33   -do { printf("ESP: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
34 40 #else
35 41 #define DPRINTF(fmt, args...)
36 42 #endif
37 43  
38   -#define ESPDMA_REGS 4
39   -#define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1)
40 44 #define ESP_MAXREG 0x3f
41 45 #define TI_BUFSZ 32
42   -#define DMA_VER 0xa0000000
43   -#define DMA_INTR 1
44   -#define DMA_INTREN 0x10
45   -#define DMA_WRITE_MEM 0x100
46   -#define DMA_LOADED 0x04000000
  46 +
47 47 typedef struct ESPState ESPState;
48 48  
49 49 struct ESPState {
50 50 BlockDriverState **bd;
51 51 uint8_t rregs[ESP_MAXREG];
52 52 uint8_t wregs[ESP_MAXREG];
53   - int irq;
54   - uint32_t espdmaregs[ESPDMA_REGS];
55   - uint32_t ti_size;
  53 + int32_t ti_size;
56 54 uint32_t ti_rptr, ti_wptr;
57 55 uint8_t ti_buf[TI_BUFSZ];
58 56 int sense;
... ... @@ -66,6 +64,7 @@ struct ESPState {
66 64 uint32_t dma_left;
67 65 uint8_t *async_buf;
68 66 uint32_t async_len;
  67 + void *dma_opaque;
69 68 };
70 69  
71 70 #define STAT_DO 0x00
... ... @@ -97,9 +96,7 @@ static int get_cmd(ESPState *s, uint8_t *buf)
97 96 target = s->wregs[4] & 7;
98 97 DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
99 98 if (s->dma) {
100   - DPRINTF("DMA Direction: %c, addr 0x%8.8x\n",
101   - s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->espdmaregs[1]);
102   - sparc_iommu_memory_read(s->espdmaregs[1], buf, dmalen);
  99 + espdma_memory_read(s->dma_opaque, buf, dmalen);
103 100 } else {
104 101 buf[0] = 0;
105 102 memcpy(&buf[1], s->ti_buf, dmalen);
... ... @@ -116,13 +113,12 @@ static int get_cmd(ESPState *s, uint8_t *buf)
116 113 s->async_len = 0;
117 114 }
118 115  
119   - if (target >= 4 || !s->scsi_dev[target]) {
  116 + if (target >= MAX_DISKS || !s->scsi_dev[target]) {
120 117 // No such drive
121 118 s->rregs[4] = STAT_IN;
122 119 s->rregs[5] = INTR_DC;
123 120 s->rregs[6] = SEQ_0;
124   - s->espdmaregs[0] |= DMA_INTR;
125   - pic_set_irq(s->irq, 1);
  121 + espdma_raise_irq(s->dma_opaque);
126 122 return 0;
127 123 }
128 124 s->current_dev = s->scsi_dev[target];
... ... @@ -137,25 +133,21 @@ static void do_cmd(ESPState *s, uint8_t *buf)
137 133 DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
138 134 lun = buf[0] & 7;
139 135 datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
140   - if (datalen == 0) {
141   - s->ti_size = 0;
142   - } else {
  136 + s->ti_size = datalen;
  137 + if (datalen != 0) {
143 138 s->rregs[4] = STAT_IN | STAT_TC;
144 139 s->dma_left = 0;
145 140 if (datalen > 0) {
146 141 s->rregs[4] |= STAT_DI;
147   - s->ti_size = datalen;
148 142 scsi_read_data(s->current_dev, 0);
149 143 } else {
150 144 s->rregs[4] |= STAT_DO;
151   - s->ti_size = -datalen;
152 145 scsi_write_data(s->current_dev, 0);
153 146 }
154 147 }
155 148 s->rregs[5] = INTR_BS | INTR_FC;
156 149 s->rregs[6] = SEQ_CD;
157   - s->espdmaregs[0] |= DMA_INTR;
158   - pic_set_irq(s->irq, 1);
  150 + espdma_raise_irq(s->dma_opaque);
159 151 }
160 152  
161 153 static void handle_satn(ESPState *s)
... ... @@ -174,12 +166,10 @@ static void handle_satn_stop(ESPState *s)
174 166 if (s->cmdlen) {
175 167 DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
176 168 s->do_cmd = 1;
177   - s->espdmaregs[1] += s->cmdlen;
178 169 s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
179 170 s->rregs[5] = INTR_BS | INTR_FC;
180 171 s->rregs[6] = SEQ_CD;
181   - s->espdmaregs[0] |= DMA_INTR;
182   - pic_set_irq(s->irq, 1);
  172 + espdma_raise_irq(s->dma_opaque);
183 173 }
184 174 }
185 175  
... ... @@ -189,9 +179,7 @@ static void write_response(ESPState *s)
189 179 s->ti_buf[0] = s->sense;
190 180 s->ti_buf[1] = 0;
191 181 if (s->dma) {
192   - DPRINTF("DMA Direction: %c\n",
193   - s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r');
194   - sparc_iommu_memory_write(s->espdmaregs[1], s->ti_buf, 2);
  182 + espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
195 183 s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
196 184 s->rregs[5] = INTR_BS | INTR_FC;
197 185 s->rregs[6] = SEQ_CD;
... ... @@ -201,9 +189,7 @@ static void write_response(ESPState *s)
201 189 s->ti_wptr = 0;
202 190 s->rregs[7] = 2;
203 191 }
204   - s->espdmaregs[0] |= DMA_INTR;
205   - pic_set_irq(s->irq, 1);
206   -
  192 + espdma_raise_irq(s->dma_opaque);
207 193 }
208 194  
209 195 static void esp_dma_done(ESPState *s)
... ... @@ -212,24 +198,19 @@ static void esp_dma_done(ESPState *s)
212 198 s->rregs[5] = INTR_BS;
213 199 s->rregs[6] = 0;
214 200 s->rregs[7] = 0;
215   - s->espdmaregs[0] |= DMA_INTR;
216   - pic_set_irq(s->irq, 1);
  201 + espdma_raise_irq(s->dma_opaque);
217 202 }
218 203  
219 204 static void esp_do_dma(ESPState *s)
220 205 {
221   - uint32_t addr, len;
  206 + uint32_t len;
222 207 int to_device;
223 208  
224   - to_device = (s->espdmaregs[0] & DMA_WRITE_MEM) == 0;
225   - addr = s->espdmaregs[1];
  209 + to_device = (s->ti_size < 0);
226 210 len = s->dma_left;
227   - DPRINTF("DMA address %08x len %08x\n", addr, len);
228 211 if (s->do_cmd) {
229   - s->espdmaregs[1] += len;
230   - s->ti_size -= len;
231 212 DPRINTF("command len %d + %d\n", s->cmdlen, len);
232   - sparc_iommu_memory_read(addr, &s->cmdbuf[s->cmdlen], len);
  213 + espdma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
233 214 s->ti_size = 0;
234 215 s->cmdlen = 0;
235 216 s->do_cmd = 0;
... ... @@ -244,19 +225,20 @@ static void esp_do_dma(ESPState *s)
244 225 len = s->async_len;
245 226 }
246 227 if (to_device) {
247   - sparc_iommu_memory_read(addr, s->async_buf, len);
  228 + espdma_memory_read(s->dma_opaque, s->async_buf, len);
248 229 } else {
249   - sparc_iommu_memory_write(addr, s->async_buf, len);
  230 + espdma_memory_write(s->dma_opaque, s->async_buf, len);
250 231 }
251   - s->ti_size -= len;
252 232 s->dma_left -= len;
253 233 s->async_buf += len;
254 234 s->async_len -= len;
255   - s->espdmaregs[1] += len;
256 235 if (s->async_len == 0) {
257 236 if (to_device) {
  237 + // ti_size is negative
  238 + s->ti_size += len;
258 239 scsi_write_data(s->current_dev, 0);
259 240 } else {
  241 + s->ti_size -= len;
260 242 scsi_read_data(s->current_dev, 0);
261 243 }
262 244 }
... ... @@ -303,6 +285,8 @@ static void handle_ti(ESPState *s)
303 285  
304 286 if (s->do_cmd)
305 287 minlen = (dmalen < 32) ? dmalen : 32;
  288 + else if (s->ti_size < 0)
  289 + minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
306 290 else
307 291 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
308 292 DPRINTF("Transfer Information len %d\n", minlen);
... ... @@ -320,13 +304,13 @@ static void handle_ti(ESPState *s)
320 304 }
321 305 }
322 306  
323   -static void esp_reset(void *opaque)
  307 +void esp_reset(void *opaque)
324 308 {
325 309 ESPState *s = opaque;
  310 +
326 311 memset(s->rregs, 0, ESP_MAXREG);
327 312 memset(s->wregs, 0, ESP_MAXREG);
328 313 s->rregs[0x0e] = 0x4; // Indicate fas100a
329   - memset(s->espdmaregs, 0, ESPDMA_REGS * 4);
330 314 s->ti_size = 0;
331 315 s->ti_rptr = 0;
332 316 s->ti_wptr = 0;
... ... @@ -353,7 +337,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
353 337 } else {
354 338 s->rregs[2] = s->ti_buf[s->ti_rptr++];
355 339 }
356   - pic_set_irq(s->irq, 1);
  340 + espdma_raise_irq(s->dma_opaque);
357 341 }
358 342 if (s->ti_size == 0) {
359 343 s->ti_rptr = 0;
... ... @@ -364,8 +348,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
364 348 // interrupt
365 349 // Clear interrupt/error status bits
366 350 s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
367   - pic_set_irq(s->irq, 0);
368   - s->espdmaregs[0] &= ~DMA_INTR;
  351 + espdma_clear_irq(s->dma_opaque);
369 352 break;
370 353 default:
371 354 break;
... ... @@ -426,8 +409,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
426 409 DPRINTF("Bus reset (%2.2x)\n", val);
427 410 s->rregs[5] = INTR_RST;
428 411 if (!(s->wregs[8] & 0x40)) {
429   - s->espdmaregs[0] |= DMA_INTR;
430   - pic_set_irq(s->irq, 1);
  412 + espdma_raise_irq(s->dma_opaque);
431 413 }
432 414 break;
433 415 case 0x10:
... ... @@ -490,68 +472,12 @@ static CPUWriteMemoryFunc *esp_mem_write[3] = {
490 472 esp_mem_writeb,
491 473 };
492 474  
493   -static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr)
494   -{
495   - ESPState *s = opaque;
496   - uint32_t saddr;
497   -
498   - saddr = (addr & ESPDMA_MAXADDR) >> 2;
499   - DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->espdmaregs[saddr]);
500   -
501   - return s->espdmaregs[saddr];
502   -}
503   -
504   -static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
505   -{
506   - ESPState *s = opaque;
507   - uint32_t saddr;
508   -
509   - saddr = (addr & ESPDMA_MAXADDR) >> 2;
510   - DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->espdmaregs[saddr], val);
511   - switch (saddr) {
512   - case 0:
513   - if (!(val & DMA_INTREN))
514   - pic_set_irq(s->irq, 0);
515   - if (val & 0x80) {
516   - esp_reset(s);
517   - } else if (val & 0x40) {
518   - val &= ~0x40;
519   - } else if (val == 0)
520   - val = 0x40;
521   - val &= 0x0fffffff;
522   - val |= DMA_VER;
523   - break;
524   - case 1:
525   - s->espdmaregs[0] |= DMA_LOADED;
526   - break;
527   - default:
528   - break;
529   - }
530   - s->espdmaregs[saddr] = val;
531   -}
532   -
533   -static CPUReadMemoryFunc *espdma_mem_read[3] = {
534   - espdma_mem_readl,
535   - espdma_mem_readl,
536   - espdma_mem_readl,
537   -};
538   -
539   -static CPUWriteMemoryFunc *espdma_mem_write[3] = {
540   - espdma_mem_writel,
541   - espdma_mem_writel,
542   - espdma_mem_writel,
543   -};
544   -
545 475 static void esp_save(QEMUFile *f, void *opaque)
546 476 {
547 477 ESPState *s = opaque;
548   - unsigned int i;
549 478  
550 479 qemu_put_buffer(f, s->rregs, ESP_MAXREG);
551 480 qemu_put_buffer(f, s->wregs, ESP_MAXREG);
552   - qemu_put_be32s(f, &s->irq);
553   - for (i = 0; i < ESPDMA_REGS; i++)
554   - qemu_put_be32s(f, &s->espdmaregs[i]);
555 481 qemu_put_be32s(f, &s->ti_size);
556 482 qemu_put_be32s(f, &s->ti_rptr);
557 483 qemu_put_be32s(f, &s->ti_wptr);
... ... @@ -562,16 +488,12 @@ static void esp_save(QEMUFile *f, void *opaque)
562 488 static int esp_load(QEMUFile *f, void *opaque, int version_id)
563 489 {
564 490 ESPState *s = opaque;
565   - unsigned int i;
566 491  
567   - if (version_id != 1)
568   - return -EINVAL;
  492 + if (version_id != 2)
  493 + return -EINVAL; // Cannot emulate 1
569 494  
570 495 qemu_get_buffer(f, s->rregs, ESP_MAXREG);
571 496 qemu_get_buffer(f, s->wregs, ESP_MAXREG);
572   - qemu_get_be32s(f, &s->irq);
573   - for (i = 0; i < ESPDMA_REGS; i++)
574   - qemu_get_be32s(f, &s->espdmaregs[i]);
575 497 qemu_get_be32s(f, &s->ti_size);
576 498 qemu_get_be32s(f, &s->ti_rptr);
577 499 qemu_get_be32s(f, &s->ti_wptr);
... ... @@ -581,28 +503,25 @@ static int esp_load(QEMUFile *f, void *opaque, int version_id)
581 503 return 0;
582 504 }
583 505  
584   -void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr)
  506 +void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque)
585 507 {
586 508 ESPState *s;
587   - int esp_io_memory, espdma_io_memory;
  509 + int esp_io_memory;
588 510 int i;
589 511  
590 512 s = qemu_mallocz(sizeof(ESPState));
591 513 if (!s)
592   - return;
  514 + return NULL;
593 515  
594 516 s->bd = bd;
595   - s->irq = irq;
  517 + s->dma_opaque = dma_opaque;
596 518  
597 519 esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
598 520 cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
599 521  
600   - espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
601   - cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
602   -
603 522 esp_reset(s);
604 523  
605   - register_savevm("esp", espaddr, 1, esp_save, esp_load, s);
  524 + register_savevm("esp", espaddr, 2, esp_save, esp_load, s);
606 525 qemu_register_reset(esp_reset, s);
607 526 for (i = 0; i < MAX_DISKS; i++) {
608 527 if (bs_table[i]) {
... ... @@ -611,5 +530,6 @@ void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdadd
611 530 scsi_disk_init(bs_table[i], 0, esp_command_complete, s);
612 531 }
613 532 }
614   -}
615 533  
  534 + return s;
  535 +}
... ...
hw/iommu.c
  View file @67e999b
... ... @@ -206,19 +206,11 @@ static uint32_t iommu_translate_pa(IOMMUState *s, uint32_t addr, uint32_t pa)
206 206 return pa;
207 207 }
208 208  
209   -uint32_t iommu_translate_local(void *opaque, uint32_t addr)
210   -{
211   - uint32_t flags;
212   - flags = iommu_page_get_flags(opaque, addr);
213   - return iommu_translate_pa(opaque, addr, flags);
214   -}
215   -
216   -void sparc_iommu_memory_rw_local(void *opaque, target_phys_addr_t addr,
217   - uint8_t *buf, int len, int is_write)
  209 +void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
  210 + uint8_t *buf, int len, int is_write)
218 211 {
219 212 int l, flags;
220 213 target_ulong page, phys_addr;
221   - void * p;
222 214  
223 215 while (len > 0) {
224 216 page = addr & TARGET_PAGE_MASK;
... ...
hw/sparc32_dma.c 0 → 100644
  View file @67e999b
  1 +/*
  2 + * QEMU Sparc32 DMA controller emulation
  3 + *
  4 + * Copyright (c) 2006 Fabrice Bellard
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +#include "vl.h"
  25 +
  26 +/* debug DMA */
  27 +//#define DEBUG_DMA
  28 +
  29 +/*
  30 + * This is the DMA controller part of chip STP2000 (Master I/O), also
  31 + * produced as NCR89C100. See
  32 + * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  33 + * and
  34 + * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  35 + */
  36 +
  37 +#ifdef DEBUG_DMA
  38 +#define DPRINTF(fmt, args...) \
  39 +do { printf("DMA: " fmt , ##args); } while (0)
  40 +#define pic_set_irq_new(ctl, irq, level) \
  41 + do { printf("DMA: set_irq(%d): %d\n", (irq), (level)); \
  42 + pic_set_irq_new((ctl), (irq),(level));} while (0)
  43 +#else
  44 +#define DPRINTF(fmt, args...)
  45 +#endif
  46 +
  47 +#define DMA_REGS 8
  48 +#define DMA_MAXADDR (DMA_REGS * 4 - 1)
  49 +
  50 +#define DMA_VER 0xa0000000
  51 +#define DMA_INTR 1
  52 +#define DMA_INTREN 0x10
  53 +#define DMA_WRITE_MEM 0x100
  54 +#define DMA_LOADED 0x04000000
  55 +#define DMA_RESET 0x80
  56 +
  57 +typedef struct DMAState DMAState;
  58 +
  59 +struct DMAState {
  60 + uint32_t dmaregs[DMA_REGS];
  61 + int espirq, leirq;
  62 + void *iommu, *esp_opaque, *lance_opaque, *intctl;
  63 +};
  64 +
  65 +void ledma_set_irq(void *opaque, int isr)
  66 +{
  67 + DMAState *s = opaque;
  68 +
  69 + pic_set_irq_new(s->intctl, s->leirq, isr);
  70 +}
  71 +
  72 +void ledma_memory_read(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len)
  73 +{
  74 + DMAState *s = opaque;
  75 +
  76 + DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
  77 + s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  78 + sparc_iommu_memory_read(s->iommu, addr | s->dmaregs[7], buf, len);
  79 +}
  80 +
  81 +void ledma_memory_write(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len)
  82 +{
  83 + DMAState *s = opaque;
  84 +
  85 + DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
  86 + s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  87 + sparc_iommu_memory_write(s->iommu, addr | s->dmaregs[7], buf, len);
  88 +}
  89 +
  90 +void espdma_raise_irq(void *opaque)
  91 +{
  92 + DMAState *s = opaque;
  93 +
  94 + s->dmaregs[0] |= DMA_INTR;
  95 + pic_set_irq_new(s->intctl, s->espirq, 1);
  96 +}
  97 +
  98 +void espdma_clear_irq(void *opaque)
  99 +{
  100 + DMAState *s = opaque;
  101 +
  102 + s->dmaregs[0] &= ~DMA_INTR;
  103 + pic_set_irq_new(s->intctl, s->espirq, 0);
  104 +}
  105 +
  106 +void espdma_memory_read(void *opaque, uint8_t *buf, int len)
  107 +{
  108 + DMAState *s = opaque;
  109 +
  110 + DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
  111 + s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  112 + sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
  113 + s->dmaregs[0] |= DMA_INTR;
  114 + s->dmaregs[1] += len;
  115 +}
  116 +
  117 +void espdma_memory_write(void *opaque, uint8_t *buf, int len)
  118 +{
  119 + DMAState *s = opaque;
  120 +
  121 + DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
  122 + s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  123 + sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
  124 + s->dmaregs[0] |= DMA_INTR;
  125 + s->dmaregs[1] += len;
  126 +}
  127 +
  128 +static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
  129 +{
  130 + DMAState *s = opaque;
  131 + uint32_t saddr;
  132 +
  133 + saddr = (addr & DMA_MAXADDR) >> 2;
  134 + DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->dmaregs[saddr]);
  135 +
  136 + return s->dmaregs[saddr];
  137 +}
  138 +
  139 +static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  140 +{
  141 + DMAState *s = opaque;
  142 + uint32_t saddr;
  143 +
  144 + saddr = (addr & DMA_MAXADDR) >> 2;
  145 + DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val);
  146 + switch (saddr) {
  147 + case 0:
  148 + if (!(val & DMA_INTREN))
  149 + pic_set_irq_new(s->intctl, s->espirq, 0);
  150 + if (val & DMA_RESET) {
  151 + esp_reset(s->esp_opaque);
  152 + } else if (val & 0x40) {
  153 + val &= ~0x40;
  154 + } else if (val == 0)
  155 + val = 0x40;
  156 + val &= 0x0fffffff;
  157 + val |= DMA_VER;
  158 + break;
  159 + case 1:
  160 + s->dmaregs[0] |= DMA_LOADED;
  161 + break;
  162 + case 4:
  163 + if (!(val & DMA_INTREN))
  164 + pic_set_irq_new(s->intctl, s->leirq, 0);
  165 + if (val & DMA_RESET)
  166 + pcnet_h_reset(s->lance_opaque);
  167 + val &= 0x0fffffff;
  168 + val |= DMA_VER;
  169 + break;
  170 + default:
  171 + break;
  172 + }
  173 + s->dmaregs[saddr] = val;
  174 +}
  175 +
  176 +static CPUReadMemoryFunc *dma_mem_read[3] = {
  177 + dma_mem_readl,
  178 + dma_mem_readl,
  179 + dma_mem_readl,
  180 +};
  181 +
  182 +static CPUWriteMemoryFunc *dma_mem_write[3] = {
  183 + dma_mem_writel,
  184 + dma_mem_writel,
  185 + dma_mem_writel,
  186 +};
  187 +
  188 +static void dma_reset(void *opaque)
  189 +{
  190 + DMAState *s = opaque;
  191 +
  192 + memset(s->dmaregs, 0, DMA_REGS * 4);
  193 + s->dmaregs[0] = DMA_VER;
  194 + s->dmaregs[4] = DMA_VER;
  195 +}
  196 +
  197 +static void dma_save(QEMUFile *f, void *opaque)
  198 +{
  199 + DMAState *s = opaque;
  200 + unsigned int i;
  201 +
  202 + for (i = 0; i < DMA_REGS; i++)
  203 + qemu_put_be32s(f, &s->dmaregs[i]);
  204 +}
  205 +
  206 +static int dma_load(QEMUFile *f, void *opaque, int version_id)
  207 +{
  208 + DMAState *s = opaque;
  209 + unsigned int i;
  210 +
  211 + if (version_id != 1)
  212 + return -EINVAL;
  213 + for (i = 0; i < DMA_REGS; i++)
  214 + qemu_get_be32s(f, &s->dmaregs[i]);
  215 +
  216 + return 0;
  217 +}
  218 +
  219 +void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu, void *intctl)
  220 +{
  221 + DMAState *s;
  222 + int dma_io_memory;
  223 +
  224 + s = qemu_mallocz(sizeof(DMAState));
  225 + if (!s)
  226 + return NULL;
  227 +
  228 + s->espirq = espirq;
  229 + s->leirq = leirq;
  230 + s->iommu = iommu;
  231 + s->intctl = intctl;
  232 +
  233 + dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
  234 + cpu_register_physical_memory(daddr, 16 * 2, dma_io_memory);
  235 +
  236 + register_savevm("sparc32_dma", daddr, 1, dma_save, dma_load, s);
  237 + qemu_register_reset(dma_reset, s);
  238 +
  239 + return s;
  240 +}
  241 +
  242 +void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
  243 + void *lance_opaque)
  244 +{
  245 + DMAState *s = opaque;
  246 +
  247 + s->esp_opaque = esp_opaque;
  248 + s->lance_opaque = lance_opaque;
  249 +}
... ...
hw/sun4m.c
  View file @67e999b
... ... @@ -37,10 +37,9 @@
37 37 #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
38 38 #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */
39 39 #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */
40   -#define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */
  40 +#define PHYS_JJ_DMA 0x78400000 /* DMA controller */
41 41 #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */
42 42 #define PHYS_JJ_ESP_IRQ 18
43   -#define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */
44 43 #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
45 44 #define PHYS_JJ_LE_IRQ 16
46 45 #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
... ... @@ -192,25 +191,6 @@ void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
192 191 slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
193 192 }
194 193  
195   -static void *iommu;
196   -
197   -uint32_t iommu_translate(uint32_t addr)
198   -{
199   - return iommu_translate_local(iommu, addr);
200   -}
201   -
202   -void sparc_iommu_memory_read(target_phys_addr_t addr,
203   - uint8_t *buf, int len)
204   -{
205   - return sparc_iommu_memory_rw_local(iommu, addr, buf, len, 0);
206   -}
207   -
208   -void sparc_iommu_memory_write(target_phys_addr_t addr,
209   - uint8_t *buf, int len)
210   -{
211   - return sparc_iommu_memory_rw_local(iommu, addr, buf, len, 1);
212   -}
213   -
214 194 static void *slavio_misc;
215 195  
216 196 void qemu_system_powerdown(void)
... ... @@ -235,6 +215,7 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
235 215 int ret, linux_boot;
236 216 unsigned int i;
237 217 long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
  218 + void *iommu, *dma, *main_esp, *main_lance = NULL;
238 219  
239 220 linux_boot = (kernel_filename != NULL);
240 221  
... ... @@ -255,12 +236,13 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
255 236 for(i = 0; i < smp_cpus; i++) {
256 237 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
257 238 }
  239 + dma = sparc32_dma_init(PHYS_JJ_DMA, PHYS_JJ_ESP_IRQ, PHYS_JJ_LE_IRQ, iommu, slavio_intctl);
258 240  
259 241 tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
260 242 if (nd_table[0].vlan) {
261 243 if (nd_table[0].model == NULL
262 244 || strcmp(nd_table[0].model, "lance") == 0) {
263   - lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
  245 + main_lance = lance_init(&nd_table[0], PHYS_JJ_LE, dma);
264 246 } else {
265 247 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
266 248 exit (1);
... ... @@ -276,8 +258,9 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
276 258 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
277 259 slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
278 260 fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
279   - esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA);
  261 + main_esp = esp_init(bs_table, PHYS_JJ_ESP, dma);
280 262 slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
  263 + sparc32_dma_set_reset_data(dma, main_esp, main_lance);
281 264  
282 265 prom_offset = ram_size + vram_size;
283 266 cpu_register_physical_memory(PROM_ADDR,
... ...
... ... @@ -924,6 +924,9 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd);
924 924 /* pcnet.c */
925 925  
926 926 void pci_pcnet_init(PCIBus *bus, NICInfo *nd);
  927 +void pcnet_h_reset(void *opaque);
  928 +void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque);
  929 +
927 930  
928 931 /* pckbd.c */
929 932  
... ... @@ -1027,22 +1030,24 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1027 1030 /* sun4m.c */
1028 1031 extern QEMUMachine sun4m_machine;
1029 1032 void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
1030   -/* ??? Remove iommu_translate once lance emulation has been converted. */
1031   -uint32_t iommu_translate(uint32_t addr);
1032   -void sparc_iommu_memory_read(target_phys_addr_t addr,
1033   - uint8_t *buf, int len);
1034   -void sparc_iommu_memory_write(target_phys_addr_t addr,
1035   - uint8_t *buf, int len);
1036 1033  
1037 1034 /* iommu.c */
1038 1035 void *iommu_init(uint32_t addr);
1039   -/* ??? Remove iommu_translate_local. */
1040   -uint32_t iommu_translate_local(void *opaque, uint32_t addr);
1041   -void sparc_iommu_memory_rw_local(void *opaque, target_phys_addr_t addr,
  1036 +void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1042 1037 uint8_t *buf, int len, int is_write);
  1038 +static inline void sparc_iommu_memory_read(void *opaque,
  1039 + target_phys_addr_t addr,
  1040 + uint8_t *buf, int len)
  1041 +{
  1042 + sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
  1043 +}
1043 1044  
1044   -/* lance.c */
1045   -void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr);
  1045 +static inline void sparc_iommu_memory_write(void *opaque,
  1046 + target_phys_addr_t addr,
  1047 + uint8_t *buf, int len)
  1048 +{
  1049 + sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
  1050 +}
1046 1051  
1047 1052 /* tcx.c */
1048 1053 void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
... ... @@ -1074,7 +1079,23 @@ void *slavio_misc_init(uint32_t base, int irq);
1074 1079 void slavio_set_power_fail(void *opaque, int power_failing);
1075 1080  
1076 1081 /* esp.c */
1077   -void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr);
  1082 +void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
  1083 +void esp_reset(void *opaque);
  1084 +
  1085 +/* sparc32_dma.c */
  1086 +void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu,
  1087 + void *intctl);
  1088 +void ledma_set_irq(void *opaque, int isr);
  1089 +void ledma_memory_read(void *opaque, target_phys_addr_t addr, uint8_t *buf,
  1090 + int len);
  1091 +void ledma_memory_write(void *opaque, target_phys_addr_t addr, uint8_t *buf,
  1092 + int len);
  1093 +void espdma_raise_irq(void *opaque);
  1094 +void espdma_clear_irq(void *opaque);
  1095 +void espdma_memory_read(void *opaque, uint8_t *buf, int len);
  1096 +void espdma_memory_write(void *opaque, uint8_t *buf, int len);
  1097 +void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
  1098 + void *lance_opaque);
1078 1099  
1079 1100 /* sun4u.c */
1080 1101 extern QEMUMachine sun4u_machine;
... ...