at91: add initial support for nand IP block

Evgeniy Dushistov
1 parent f938f6b6
Showing 5 changed files with 112 additions and 12 deletions
Makefile.target
hw/at91.h
hw/at91_lcdc.c
hw/at91_nand.c
hw/at91sam9.c
@@ -411,7 +411,7 @@ obj-sparc-y += cs4231.o eccmemctl.o sbi.o sun4c_intctl.o
 endif
 obj-arm-y = integratorcp.o versatilepb.o smc91c111.o arm_pic.o arm_timer.o
-obj-arm-y += pflash_atmel.o at91sam9.o spi_flash.o at91_lcdc.o
+obj-arm-y += pflash_atmel.o at91sam9.o spi_flash.o at91_lcdc.o at91_nand.o
 obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
 obj-arm-y += versatile_pci.o
 obj-arm-y += realview_gic.o realview.o arm_sysctl.o mpcore.o
@@ -56,4 +56,6 @@ extern void at91_pdc_reset(PDCState *s);
 extern void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val);
 extern uint32_t at91_pdc_read(void *opaque, target_phys_addr_t offset);
+extern void at91_nand_register(void);
+
 #endif /* !AT91_H */
@@ -138,6 +138,18 @@ union pixel8u {
     uint8_t val;
 };
+struct pixel16 {
+    unsigned b : 5;
+    unsigned g : 5;
+    unsigned r : 5;
+};
+
+union pixel16u {
+    struct pixel16 p;
+    uint8_t val[0];
+};
+
+
 static void at91_lcdc_update_display(void *opaque)
 {
     LCDCState *s = opaque;
@@ -149,7 +161,9 @@ static void at91_lcdc_update_display(void *opaque)
     int q_bpp = (ds_get_bits_per_pixel(s->ds) + 7) >> 3;
     int bpp;
     int bpp_idx = (s->lcdcon2 >> 5) & 7;
-    union pixel8u tmp;
+    union pixel8u tmp8;
+    union pixel16u tmp16;
+    unsigned int r, g, b;
     DPRINTF("update begin\n");
     if (!(s->dmacon & DMACON_DMAEN))
@@ -167,33 +181,49 @@ static void at91_lcdc_update_display(void *opaque)
         return;//reserved value, unknown pixel size
     }
     /*TODO: fix this restriction*/
-    if (bpp != 8) {
-        fprintf(stderr, "Unsupported pixel size\n");
+    if (bpp != 8 && bpp != 16) {
+        fprintf(stderr, "Unsupported pixel size: %d\n", bpp);
         return;
     }
-    int once = 0;
+    //int once = 0;
     for (y = 0; y < height; ++y) {        
         for (x = 0; x < width; ++x) {
-            cpu_physical_memory_read(s->dmabaddr1 + width * y + x, &tmp.val, 1);
+            if (bpp == 8) {
+                cpu_physical_memory_read(s->dmabaddr1 + width * y + x, &tmp8.val, 1);
+                r = tmp8.p.r;
+                g = tmp8.p.g;
+                b = tmp8.p.b;
+            } else {
+                cpu_physical_memory_read(s->dmabaddr1 + width * y + x, &tmp16.val[0], 2);
+                r = tmp16.p.r;
+                g = tmp16.p.g;
+                b = tmp16.p.b;
+            }
+#if 0
             if (tmp.val != 0 && once == 0) {
                 once = 1;
-                DPRINTF("not null %X, %X, %X, bpp %d\n", (unsigned)tmp.p.r << 5, (unsigned)tmp.p.g << 5, (unsigned)tmp.p.b << 6, ds_get_bits_per_pixel(s->ds));
+                DPRINTF("not null %X, %X, %X, bpp %d\n", (unsigned)r << 5, (unsigned)g << 5, (unsigned)b << 6,
+                        ds_get_bits_per_pixel(s->ds));
             }
+#endif
             switch (ds_get_bits_per_pixel(s->ds)) {
             case 8:
-                color = rgb_to_pixel8(tmp.p.r, tmp.p.g, tmp.p.b);
+                color = rgb_to_pixel8(r, g, b);
                 break;
             case 15:
-                color = rgb_to_pixel15(tmp.p.r, tmp.p.g, tmp.p.b);
+                color = rgb_to_pixel15(r, g, b);
                 break;
             case 16:
-                color = rgb_to_pixel16(tmp.p.r, tmp.p.g, tmp.p.b);
+                color = rgb_to_pixel16(r, g, b);
                 break;
             case 24:
-                color = rgb_to_pixel24(tmp.p.r, tmp.p.g, tmp.p.b);
+                color = rgb_to_pixel24(r, g, b);
                 break;
             case 32:
-                color = rgb_to_pixel32((unsigned)tmp.p.r << 5, (unsigned)tmp.p.g << 5, (unsigned)tmp.p.b << 6);
+                if (bpp == 8)
+                    color = rgb_to_pixel32((unsigned)r << 5, (unsigned)g << 5, (unsigned)b << 6);
+                else
+                    color = rgb_to_pixel32((unsigned)r << 3, (unsigned)g << 3, (unsigned)b << 3);
                 break;
             default:
                 return;
+#include <stdio.h>
+
+#include "hw.h"
+#include "at91.h"
+
+typedef struct NandState {
+    unsigned int cmd;
+} NandState;
+
+#define AT91_NAND_DEBUG
+#ifdef AT91_NAND_DEBUG
+#define DPRINTF(fmt, ...)                           \
+    do {                                            \
+        printf("AT91NAND: " fmt , ## __VA_ARGS__);    \
+    } while (0)
+#else
+#define DPRINTF(fmt, ...) do { } while (0)
+#endif
+
+extern CPUState *g_env;
+
+static uint32_t at91_nand_mem_read(void *opaque, target_phys_addr_t offset)
+{
+    NandState *s = opaque;
+
+    DPRINTF("(IP %X) read from %X\n", g_env->regs[15], offset);
+    switch (s->cmd) {
+    case 0x70:
+        s->cmd = 0;
+        return 0x40;
+    default:
+        return 0x0;
+    }
+}
+
+static void at91_nand_mem_write(void *opaque, target_phys_addr_t offset,
+                uint32_t value)
+{
+    NandState *s = opaque;
+
+    DPRINTF("(IP %X) write to %X %X\n", g_env->regs[15], offset, value);
+    s->cmd = value;
+}
+
+static CPUReadMemoryFunc *at91_nand_readfn[] = {
+    at91_nand_mem_read,
+    at91_nand_mem_read,
+    at91_nand_mem_read,
+};
+
+static CPUWriteMemoryFunc *at91_nand_writefn[] = {
+    at91_nand_mem_write,
+    at91_nand_mem_write,
+    at91_nand_mem_write,
+};
+
+void at91_nand_register(void)
+{
+    NandState *s;
+    int iomemtype;
+
+    s = qemu_mallocz(sizeof(*s));
+    iomemtype = cpu_register_io_memory(at91_nand_readfn, at91_nand_writefn, s);
+    cpu_register_physical_memory(0x40000000, 0x10000000, iomemtype);
+}
+
+
@@ -352,6 +352,7 @@ static void at91sam9_init(ram_addr_t ram_size,
             //rom
             cpu_register_physical_memory(0x0, 100 * 1024,
                                          sam9->bootrom | IO_MEM_ROMD);
+            at91_nand_register();
         } else {
             //nor flash
             ram_addr_t nor_flash_mem = qemu_ram_alloc(NOR_FLASH_SIZE);