gwj / at91sam9263 · Commits

Commit 66c7c80657e6b7ca42a7eb7aff28bebfef030b87

Authored by aurel32
1 parent c7eb95e1

SH: Implement MOVCO.L and MOVLI.L 

* target-sh4/cpu.h (struct CPUSH4State): New field ldst.
* target-sh4/translate.c (cpu_ldst): New.
  (sh4_translate_init): Initialize cpu_ldst.
  (_decode_opc): Support MOVCO.L and MOVLI.L.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6666 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 36 additions and 1 deletions
target-sh4/cpu.h
  View file @66c7c80
@@ -140,6 +140,8 @@ typedef struct CPUSH4State { @@ -140,6 +140,8 @@ typedef struct CPUSH4State {
140 uint32_t prr; /* Processor Revision Register */ 140 uint32_t prr; /* Processor Revision Register */
141 uint32_t cvr; /* Cache Version Register */ 141 uint32_t cvr; /* Cache Version Register */
142 142
  143 + uint32_t ldst;
  144 +
143 CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ 145 CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
144 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ 146 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
145 void *intc_handle; 147 void *intc_handle;
target-sh4/translate.c
  View file @66c7c80
@@ -72,7 +72,7 @@ static TCGv_ptr cpu_env; @@ -72,7 +72,7 @@ static TCGv_ptr cpu_env;
72 static TCGv cpu_gregs[24]; 72 static TCGv cpu_gregs[24];
73 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; 73 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
74 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; 74 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
75 -static TCGv cpu_pr, cpu_fpscr, cpu_fpul; 75 +static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst;
76 static TCGv cpu_fregs[32]; 76 static TCGv cpu_fregs[32];
77 77
78 /* internal register indexes */ 78 /* internal register indexes */
@@ -144,6 +144,8 @@ static void sh4_translate_init(void) @@ -144,6 +144,8 @@ static void sh4_translate_init(void)
144 cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, 144 cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
145 offsetof(CPUState, delayed_pc), 145 offsetof(CPUState, delayed_pc),
146 "_delayed_pc_"); 146 "_delayed_pc_");
  147 + cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0,
  148 + offsetof(CPUState, ldst), "_ldst_");
147 149
148 for (i = 0; i < 32; i++) 150 for (i = 0; i < 32; i++)
149 cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, 151 cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
@@ -1559,6 +1561,37 @@ static void _decode_opc(DisasContext * ctx) @@ -1559,6 +1561,37 @@ static void _decode_opc(DisasContext * ctx)
1559 case 0x0029: /* movt Rn */ 1561 case 0x0029: /* movt Rn */
1560 tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); 1562 tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1561 return; 1563 return;
  1564 + case 0x0073:
  1565 + /* MOVCO.L
  1566 + LDST -> T
  1567 + If (T == 1) R0 -> (Rn)
  1568 + 0 -> LDST
  1569 + */
  1570 + if (ctx->features & SH_FEATURE_SH4A) {
  1571 + int label = gen_new_label();
  1572 + gen_clr_t();
  1573 + tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
  1574 + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
  1575 + tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
  1576 + gen_set_label(label);
  1577 + tcg_gen_movi_i32(cpu_ldst, 0);
  1578 + return;
  1579 + } else
  1580 + break;
  1581 + case 0x0063:
  1582 + /* MOVLI.L @Rm,R0
  1583 + 1 -> LDST
  1584 + (Rm) -> R0
  1585 + When interrupt/exception
  1586 + occurred 0 -> LDST
  1587 + */
  1588 + if (ctx->features & SH_FEATURE_SH4A) {
  1589 + tcg_gen_movi_i32(cpu_ldst, 0);
  1590 + tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);
  1591 + tcg_gen_movi_i32(cpu_ldst, 1);
  1592 + return;
  1593 + } else
  1594 + break;
1562 case 0x0093: /* ocbi @Rn */ 1595 case 0x0093: /* ocbi @Rn */
1563 { 1596 {
1564 TCGv dummy = tcg_temp_new(); 1597 TCGv dummy = tcg_temp_new();