gwj / at91sam9263 · Commits

Commit 66ba317c90fc9b668374574e3dc4f45586f56dca

Authored by aurel32
1 parent 9850d1e8

target-sh4: map FP registers as TCG variables 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5758 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 43 additions and 106 deletions
target-sh4/translate.c
  View file @66ba317
... ... @@ -72,6 +72,7 @@ static TCGv cpu_gregs[24];
72 72 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
73 73 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
74 74 static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
  75 +static TCGv cpu_fregs[32];
75 76  
76 77 /* internal register indexes */
77 78 static TCGv cpu_flags, cpu_delayed_pc;
... ... @@ -89,6 +90,16 @@ static void sh4_translate_init(void)
89 90 "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
90 91 "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
91 92 };
  93 + static const char * const fregnames[32] = {
  94 + "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
  95 + "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
  96 + "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
  97 + "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
  98 + "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
  99 + "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
  100 + "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
  101 + "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
  102 + };
92 103  
93 104 if (done_init)
94 105 return;
... ... @@ -97,8 +108,8 @@ static void sh4_translate_init(void)
97 108  
98 109 for (i = 0; i < 24; i++)
99 110 cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
100   - offsetof(CPUState, gregs[i]),
101   - gregnames[i]);
  111 + offsetof(CPUState, gregs[i]),
  112 + gregnames[i]);
102 113  
103 114 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
104 115 offsetof(CPUState, pc), "PC");
... ... @@ -133,6 +144,11 @@ static void sh4_translate_init(void)
133 144 offsetof(CPUState, delayed_pc),
134 145 "_delayed_pc_");
135 146  
  147 + for (i = 0; i < 32; i++)
  148 + cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
  149 + offsetof(CPUState, fregs[i]),
  150 + fregnames[i]);
  151 +
136 152 /* register helpers */
137 153 #define GEN_HELPER 2
138 154 #include "helper.h"
... ... @@ -393,38 +409,19 @@ static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
393 409 tcg_temp_free(tmp);
394 410 }
395 411  
396   -
397   -static inline void gen_load_fpr32(TCGv_i32 t, int reg)
398   -{
399   - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
400   -}
401   -
402 412 static inline void gen_load_fpr64(TCGv_i64 t, int reg)
403 413 {
404   - TCGv_i32 tmp1 = tcg_temp_new_i32();
405   - TCGv_i32 tmp2 = tcg_temp_new_i32();
406   -
407   - tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
408   - tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1]));
409   - tcg_gen_concat_i32_i64(t, tmp2, tmp1);
410   - tcg_temp_free_i32(tmp1);
411   - tcg_temp_free_i32(tmp2);
412   -}
413   -
414   -static inline void gen_store_fpr32(TCGv_i32 t, int reg)
415   -{
416   - tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
  414 + tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
417 415 }
418 416  
419 417 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
420 418 {
421 419 TCGv_i32 tmp = tcg_temp_new_i32();
422   -
423 420 tcg_gen_trunc_i64_i32(tmp, t);
424   - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1]));
  421 + tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
425 422 tcg_gen_shri_i64(t, t, 32);
426 423 tcg_gen_trunc_i64_i32(tmp, t);
427   - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg]));
  424 + tcg_gen_mov_i32(cpu_fregs[reg], tmp);
428 425 tcg_temp_free_i32(tmp);
429 426 }
430 427  
... ... @@ -989,10 +986,7 @@ static void _decode_opc(DisasContext * ctx)
989 986 gen_store_fpr64(fp, XREG(B11_8));
990 987 tcg_temp_free_i64(fp);
991 988 } else {
992   - TCGv_i32 fp = tcg_temp_new_i32();
993   - gen_load_fpr32(fp, FREG(B7_4));
994   - gen_store_fpr32(fp, FREG(B11_8));
995   - tcg_temp_free_i32(fp);
  989 + tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
996 990 }
997 991 return;
998 992 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
... ... @@ -1002,10 +996,7 @@ static void _decode_opc(DisasContext * ctx)
1002 996 tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
1003 997 tcg_temp_free_i64(fp);
1004 998 } else {
1005   - TCGv_i32 fp = tcg_temp_new_i32();
1006   - gen_load_fpr32(fp, FREG(B7_4));
1007   - tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx);
1008   - tcg_temp_free_i32(fp);
  999 + tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
1009 1000 }
1010 1001 return;
1011 1002 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
... ... @@ -1015,10 +1006,7 @@ static void _decode_opc(DisasContext * ctx)
1015 1006 gen_store_fpr64(fp, XREG(B11_8));
1016 1007 tcg_temp_free_i64(fp);
1017 1008 } else {
1018   - TCGv_i32 fp = tcg_temp_new_i32();
1019   - tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1020   - gen_store_fpr32(fp, FREG(B11_8));
1021   - tcg_temp_free_i32(fp);
  1009 + tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1022 1010 }
1023 1011 return;
1024 1012 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
... ... @@ -1029,10 +1017,7 @@ static void _decode_opc(DisasContext * ctx)
1029 1017 tcg_temp_free_i64(fp);
1030 1018 tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
1031 1019 } else {
1032   - TCGv_i32 fp = tcg_temp_new_i32();
1033   - tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1034   - gen_store_fpr32(fp, FREG(B11_8));
1035   - tcg_temp_free_i32(fp);
  1020 + tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1036 1021 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1037 1022 }
1038 1023 return;
... ... @@ -1050,13 +1035,9 @@ static void _decode_opc(DisasContext * ctx)
1050 1035 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
1051 1036 } else {
1052 1037 TCGv addr;
1053   - TCGv_i32 fp;
1054 1038 addr = tcg_temp_new_i32();
1055 1039 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1056   - fp = tcg_temp_new_i32();
1057   - gen_load_fpr32(fp, FREG(B7_4));
1058   - tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1059   - tcg_temp_free_i32(fp);
  1040 + tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1060 1041 tcg_temp_free(addr);
1061 1042 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1062 1043 }
... ... @@ -1071,10 +1052,7 @@ static void _decode_opc(DisasContext * ctx)
1071 1052 gen_store_fpr64(fp, XREG(B11_8));
1072 1053 tcg_temp_free_i64(fp);
1073 1054 } else {
1074   - TCGv_i32 fp = tcg_temp_new_i32();
1075   - tcg_gen_qemu_ld32u(fp, addr, ctx->memidx);
1076   - gen_store_fpr32(fp, FREG(B11_8));
1077   - tcg_temp_free_i32(fp);
  1055 + tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
1078 1056 }
1079 1057 tcg_temp_free(addr);
1080 1058 }
... ... @@ -1089,10 +1067,7 @@ static void _decode_opc(DisasContext * ctx)
1089 1067 tcg_gen_qemu_st64(fp, addr, ctx->memidx);
1090 1068 tcg_temp_free_i64(fp);
1091 1069 } else {
1092   - TCGv_i32 fp = tcg_temp_new_i32();
1093   - gen_load_fpr32(fp, FREG(B7_4));
1094   - tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1095   - tcg_temp_free_i32(fp);
  1070 + tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1096 1071 }
1097 1072 tcg_temp_free(addr);
1098 1073 }
... ... @@ -1137,36 +1112,26 @@ static void _decode_opc(DisasContext * ctx)
1137 1112 tcg_temp_free_i64(fp0);
1138 1113 tcg_temp_free_i64(fp1);
1139 1114 } else {
1140   - TCGv_i32 fp0, fp1;
1141   -
1142   - fp0 = tcg_temp_new_i32();
1143   - fp1 = tcg_temp_new_i32();
1144   - gen_load_fpr32(fp0, FREG(B11_8));
1145   - gen_load_fpr32(fp1, FREG(B7_4));
1146   -
1147 1115 switch (ctx->opcode & 0xf00f) {
1148 1116 case 0xf000: /* fadd Rm,Rn */
1149   - gen_helper_fadd_FT(fp0, fp0, fp1);
  1117 + gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1150 1118 break;
1151 1119 case 0xf001: /* fsub Rm,Rn */
1152   - gen_helper_fsub_FT(fp0, fp0, fp1);
  1120 + gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1153 1121 break;
1154 1122 case 0xf002: /* fmul Rm,Rn */
1155   - gen_helper_fmul_FT(fp0, fp0, fp1);
  1123 + gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1156 1124 break;
1157 1125 case 0xf003: /* fdiv Rm,Rn */
1158   - gen_helper_fdiv_FT(fp0, fp0, fp1);
  1126 + gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1159 1127 break;
1160 1128 case 0xf004: /* fcmp/eq Rm,Rn */
1161   - gen_helper_fcmp_eq_FT(fp0, fp1);
  1129 + gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1162 1130 return;
1163 1131 case 0xf005: /* fcmp/gt Rm,Rn */
1164   - gen_helper_fcmp_gt_FT(fp0, fp1);
  1132 + gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1165 1133 return;
1166 1134 }
1167   - gen_store_fpr32(fp0, FREG(B11_8));
1168   - tcg_temp_free_i32(fp0);
1169   - tcg_temp_free_i32(fp1);
1170 1135 }
1171 1136 }
1172 1137 return;
... ... @@ -1633,18 +1598,12 @@ static void _decode_opc(DisasContext * ctx)
1633 1598 return;
1634 1599 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1635 1600 {
1636   - TCGv fp = tcg_temp_new();
1637   - tcg_gen_mov_i32(fp, cpu_fpul);
1638   - gen_store_fpr32(fp, FREG(B11_8));
1639   - tcg_temp_free(fp);
  1601 + tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
1640 1602 }
1641 1603 return;
1642 1604 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1643 1605 {
1644   - TCGv fp = tcg_temp_new();
1645   - gen_load_fpr32(fp, FREG(B11_8));
1646   - tcg_gen_mov_i32(cpu_fpul, fp);
1647   - tcg_temp_free(fp);
  1606 + tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1648 1607 }
1649 1608 return;
1650 1609 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
... ... @@ -1658,10 +1617,7 @@ static void _decode_opc(DisasContext * ctx)
1658 1617 tcg_temp_free_i64(fp);
1659 1618 }
1660 1619 else {
1661   - TCGv_i32 fp = tcg_temp_new_i32();
1662   - gen_helper_float_FT(fp, cpu_fpul);
1663   - gen_store_fpr32(fp, FREG(B11_8));
1664   - tcg_temp_free_i32(fp);
  1620 + gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
1665 1621 }
1666 1622 return;
1667 1623 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
... ... @@ -1675,19 +1631,12 @@ static void _decode_opc(DisasContext * ctx)
1675 1631 tcg_temp_free_i64(fp);
1676 1632 }
1677 1633 else {
1678   - TCGv_i32 fp = tcg_temp_new_i32();
1679   - gen_load_fpr32(fp, FREG(B11_8));
1680   - gen_helper_ftrc_FT(cpu_fpul, fp);
1681   - tcg_temp_free_i32(fp);
  1634 + gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1682 1635 }
1683 1636 return;
1684 1637 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1685 1638 {
1686   - TCGv_i32 fp = tcg_temp_new_i32();
1687   - gen_load_fpr32(fp, FREG(B11_8));
1688   - gen_helper_fneg_T(fp, fp);
1689   - gen_store_fpr32(fp, FREG(B11_8));
1690   - tcg_temp_free_i32(fp);
  1639 + gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1691 1640 }
1692 1641 return;
1693 1642 case 0xf05d: /* fabs FRn/DRn */
... ... @@ -1700,11 +1649,7 @@ static void _decode_opc(DisasContext * ctx)
1700 1649 gen_store_fpr64(fp, DREG(B11_8));
1701 1650 tcg_temp_free_i64(fp);
1702 1651 } else {
1703   - TCGv_i32 fp = tcg_temp_new_i32();
1704   - gen_load_fpr32(fp, FREG(B11_8));
1705   - gen_helper_fabs_FT(fp, fp);
1706   - gen_store_fpr32(fp, FREG(B11_8));
1707   - tcg_temp_free_i32(fp);
  1652 + gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1708 1653 }
1709 1654 return;
1710 1655 case 0xf06d: /* fsqrt FRn */
... ... @@ -1717,28 +1662,20 @@ static void _decode_opc(DisasContext * ctx)
1717 1662 gen_store_fpr64(fp, DREG(B11_8));
1718 1663 tcg_temp_free_i64(fp);
1719 1664 } else {
1720   - TCGv_i32 fp = tcg_temp_new_i32();
1721   - gen_load_fpr32(fp, FREG(B11_8));
1722   - gen_helper_fsqrt_FT(fp, fp);
1723   - gen_store_fpr32(fp, FREG(B11_8));
1724   - tcg_temp_free_i32(fp);
  1665 + gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1725 1666 }
1726 1667 return;
1727 1668 case 0xf07d: /* fsrra FRn */
1728 1669 break;
1729 1670 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1730 1671 if (!(ctx->fpscr & FPSCR_PR)) {
1731   - TCGv_i32 val = tcg_const_i32(0);
1732   - gen_load_fpr32(val, FREG(B11_8));
1733   - tcg_temp_free_i32(val);
  1672 + tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
1734 1673 return;
1735 1674 }
1736 1675 break;
1737 1676 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1738 1677 if (!(ctx->fpscr & FPSCR_PR)) {
1739   - TCGv_i32 val = tcg_const_i32(0x3f800000);
1740   - gen_load_fpr32(val, FREG(B11_8));
1741   - tcg_temp_free_i32(val);
  1678 + tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
1742 1679 return;
1743 1680 }
1744 1681 break;
... ...