gwj / at91sam9263 · Commits

Commit 66896cb803b4865c0c35b218dbc407e1fcf7f7f7

Authored by aurel32
1 parent 537a1d4b

tcg: rename bswap_i32/i64 functions 

Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 13 changed files with 47 additions and 47 deletions
target-arm/translate.c
  View file @66896cb
... ... @@ -5162,7 +5162,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
5162 5162 NEON_GET_REG(T0, rm, pass * 2);
5163 5163 NEON_GET_REG(T1, rm, pass * 2 + 1);
5164 5164 switch (size) {
5165   - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
  5165 + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break;
5166 5166 case 1: gen_swap_half(cpu_T[0]); break;
5167 5167 case 2: /* no-op */ break;
5168 5168 default: abort();
... ... @@ -5173,7 +5173,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
5173 5173 } else {
5174 5174 gen_op_movl_T0_T1();
5175 5175 switch (size) {
5176   - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
  5176 + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break;
5177 5177 case 1: gen_swap_half(cpu_T[0]); break;
5178 5178 default: abort();
5179 5179 }
... ... @@ -5315,7 +5315,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
5315 5315 switch (op) {
5316 5316 case 1: /* VREV32 */
5317 5317 switch (size) {
5318   - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break;
  5318 + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break;
5319 5319 case 1: gen_swap_half(cpu_T[0]); break;
5320 5320 default: return 1;
5321 5321 }
... ... @@ -6568,7 +6568,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
6568 6568 if (insn & (1 << 7))
6569 6569 gen_rev16(tmp);
6570 6570 else
6571   - tcg_gen_bswap_i32(tmp, tmp);
  6571 + tcg_gen_bswap32_i32(tmp, tmp);
6572 6572 }
6573 6573 store_reg(s, rd, tmp);
6574 6574 } else {
... ... @@ -7384,7 +7384,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7384 7384 gen_helper_rbit(tmp, tmp);
7385 7385 break;
7386 7386 case 0x08: /* rev */
7387   - tcg_gen_bswap_i32(tmp, tmp);
  7387 + tcg_gen_bswap32_i32(tmp, tmp);
7388 7388 break;
7389 7389 case 0x09: /* rev16 */
7390 7390 gen_rev16(tmp);
... ... @@ -8518,7 +8518,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
8518 8518 rd = insn & 0x7;
8519 8519 tmp = load_reg(s, rn);
8520 8520 switch ((insn >> 6) & 3) {
8521   - case 0: tcg_gen_bswap_i32(tmp, tmp); break;
  8521 + case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
8522 8522 case 1: gen_rev16(tmp); break;
8523 8523 case 3: gen_revsh(tmp); break;
8524 8524 default: goto illegal_op;
... ...
target-i386/translate.c
  View file @66896cb
... ... @@ -6640,7 +6640,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
6640 6640 #ifdef TARGET_X86_64
6641 6641 if (dflag == 2) {
6642 6642 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6643   - tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]);
  6643 + tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6644 6644 gen_op_mov_reg_T0(OT_QUAD, reg);
6645 6645 } else
6646 6646 {
... ... @@ -6649,14 +6649,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
6649 6649  
6650 6650 tmp0 = tcg_temp_new_i32();
6651 6651 tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
6652   - tcg_gen_bswap_i32(tmp0, tmp0);
  6652 + tcg_gen_bswap32_i32(tmp0, tmp0);
6653 6653 tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
6654 6654 gen_op_mov_reg_T0(OT_LONG, reg);
6655 6655 }
6656 6656 #else
6657 6657 {
6658 6658 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6659   - tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]);
  6659 + tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]);
6660 6660 gen_op_mov_reg_T0(OT_LONG, reg);
6661 6661 }
6662 6662 #endif
... ...
target-m68k/translate.c
  View file @66896cb
... ... @@ -1247,7 +1247,7 @@ DISAS_INSN(byterev)
1247 1247 TCGv reg;
1248 1248  
1249 1249 reg = DREG(insn, 0);
1250   - tcg_gen_bswap_i32(reg, reg);
  1250 + tcg_gen_bswap32_i32(reg, reg);
1251 1251 }
1252 1252  
1253 1253 DISAS_INSN(move)
... ...
target-ppc/translate.c
  View file @66896cb
... ... @@ -2621,11 +2621,11 @@ static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2
2621 2621 #if defined(TARGET_PPC64)
2622 2622 TCGv_i32 t0 = tcg_temp_new_i32();
2623 2623 tcg_gen_trunc_tl_i32(t0, arg1);
2624   - tcg_gen_bswap_i32(t0, t0);
  2624 + tcg_gen_bswap32_i32(t0, t0);
2625 2625 tcg_gen_extu_i32_tl(arg1, t0);
2626 2626 tcg_temp_free_i32(t0);
2627 2627 #else
2628   - tcg_gen_bswap_i32(arg1, arg1);
  2628 + tcg_gen_bswap32_i32(arg1, arg1);
2629 2629 #endif
2630 2630 }
2631 2631 }
... ... @@ -2638,7 +2638,7 @@ static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2
2638 2638 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2639 2639 t0 = tcg_temp_new_i32();
2640 2640 tcg_gen_trunc_tl_i32(t0, arg1);
2641   - tcg_gen_bswap_i32(t0, t0);
  2641 + tcg_gen_bswap32_i32(t0, t0);
2642 2642 tcg_gen_ext_i32_tl(arg1, t0);
2643 2643 tcg_temp_free_i32(t0);
2644 2644 } else
... ... @@ -2650,7 +2650,7 @@ static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv a
2650 2650 {
2651 2651 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2652 2652 if (unlikely(ctx->le_mode)) {
2653   - tcg_gen_bswap_i64(arg1, arg1);
  2653 + tcg_gen_bswap64_i64(arg1, arg1);
2654 2654 }
2655 2655 }
2656 2656  
... ... @@ -2694,7 +2694,7 @@ static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2694 2694 TCGv t1;
2695 2695 t0 = tcg_temp_new_i32();
2696 2696 tcg_gen_trunc_tl_i32(t0, arg1);
2697   - tcg_gen_bswap_i32(t0, t0);
  2697 + tcg_gen_bswap32_i32(t0, t0);
2698 2698 t1 = tcg_temp_new();
2699 2699 tcg_gen_extu_i32_tl(t1, t0);
2700 2700 tcg_temp_free_i32(t0);
... ... @@ -2702,7 +2702,7 @@ static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2702 2702 tcg_temp_free(t1);
2703 2703 #else
2704 2704 TCGv t0 = tcg_temp_new_i32();
2705   - tcg_gen_bswap_i32(t0, arg1);
  2705 + tcg_gen_bswap32_i32(t0, arg1);
2706 2706 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2707 2707 tcg_temp_free(t0);
2708 2708 #endif
... ... @@ -2715,7 +2715,7 @@ static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv a
2715 2715 {
2716 2716 if (unlikely(ctx->le_mode)) {
2717 2717 TCGv_i64 t0 = tcg_temp_new_i64();
2718   - tcg_gen_bswap_i64(t0, arg1);
  2718 + tcg_gen_bswap64_i64(t0, arg1);
2719 2719 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2720 2720 tcg_temp_free_i64(t0);
2721 2721 } else
... ... @@ -3014,11 +3014,11 @@ static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg
3014 3014 #if defined(TARGET_PPC64)
3015 3015 TCGv_i32 t0 = tcg_temp_new_i32();
3016 3016 tcg_gen_trunc_tl_i32(t0, arg1);
3017   - tcg_gen_bswap_i32(t0, t0);
  3017 + tcg_gen_bswap32_i32(t0, t0);
3018 3018 tcg_gen_extu_i32_tl(arg1, t0);
3019 3019 tcg_temp_free_i32(t0);
3020 3020 #else
3021   - tcg_gen_bswap_i32(arg1, arg1);
  3021 + tcg_gen_bswap32_i32(arg1, arg1);
3022 3022 #endif
3023 3023 }
3024 3024 }
... ... @@ -3062,7 +3062,7 @@ static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2
3062 3062 TCGv t1;
3063 3063 t0 = tcg_temp_new_i32();
3064 3064 tcg_gen_trunc_tl_i32(t0, arg1);
3065   - tcg_gen_bswap_i32(t0, t0);
  3065 + tcg_gen_bswap32_i32(t0, t0);
3066 3066 t1 = tcg_temp_new();
3067 3067 tcg_gen_extu_i32_tl(t1, t0);
3068 3068 tcg_temp_free_i32(t0);
... ... @@ -3070,7 +3070,7 @@ static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2
3070 3070 tcg_temp_free(t1);
3071 3071 #else
3072 3072 TCGv t0 = tcg_temp_new_i32();
3073   - tcg_gen_bswap_i32(t0, arg1);
  3073 + tcg_gen_bswap32_i32(t0, arg1);
3074 3074 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3075 3075 tcg_temp_free(t0);
3076 3076 #endif
... ...
tcg/arm/tcg-target.h
  View file @66896cb
... ... @@ -28,7 +28,7 @@
28 28 #undef TCG_TARGET_WORDS_BIGENDIAN
29 29 #undef TCG_TARGET_HAS_div_i32
30 30 #undef TCG_TARGET_HAS_div_i64
31   -#undef TCG_TARGET_HAS_bswap_i32
  31 +#undef TCG_TARGET_HAS_bswap32_i32
32 32 #define TCG_TARGET_HAS_ext8s_i32
33 33 #define TCG_TARGET_HAS_ext16s_i32
34 34 #define TCG_TARGET_HAS_neg_i32
... ...
tcg/hppa/tcg-target.h
  View file @66896cb
... ... @@ -78,7 +78,7 @@ enum {
78 78 //#define TCG_TARGET_HAS_ext8s_i32
79 79 //#define TCG_TARGET_HAS_ext16s_i32
80 80 //#define TCG_TARGET_HAS_bswap16_i32
81   -//#define TCG_TARGET_HAS_bswap_i32
  81 +//#define TCG_TARGET_HAS_bswap32_i32
82 82  
83 83 /* Note: must be synced with dyngen-exec.h */
84 84 #define TCG_AREG0 TCG_REG_R17
... ...
tcg/i386/tcg-target.c
  View file @66896cb
... ... @@ -1034,7 +1034,7 @@ static inline void tcg_out_op(TCGContext *s, int opc,
1034 1034 tcg_out_brcond2(s, args, const_args);
1035 1035 break;
1036 1036  
1037   - case INDEX_op_bswap_i32:
  1037 + case INDEX_op_bswap32_i32:
1038 1038 tcg_out_opc(s, (0xc8 + args[0]) | P_EXT);
1039 1039 break;
1040 1040  
... ... @@ -1130,7 +1130,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
1130 1130 { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1131 1131 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1132 1132  
1133   - { INDEX_op_bswap_i32, { "r", "0" } },
  1133 + { INDEX_op_bswap32_i32, { "r", "0" } },
1134 1134  
1135 1135 { INDEX_op_neg_i32, { "r", "0" } },
1136 1136  
... ...
tcg/i386/tcg-target.h
  View file @66896cb
... ... @@ -45,7 +45,7 @@ enum {
45 45 #define TCG_TARGET_CALL_STACK_OFFSET 0
46 46  
47 47 /* optional instructions */
48   -#define TCG_TARGET_HAS_bswap_i32
  48 +#define TCG_TARGET_HAS_bswap32_i32
49 49 #define TCG_TARGET_HAS_neg_i32
50 50 #define TCG_TARGET_HAS_not_i32
51 51 #define TCG_TARGET_HAS_ext8s_i32
... ...
tcg/sparc/tcg-target.h
  View file @66896cb
... ... @@ -86,8 +86,8 @@ enum {
86 86 #endif
87 87  
88 88 /* optional instructions */
89   -//#define TCG_TARGET_HAS_bswap_i32
90   -//#define TCG_TARGET_HAS_bswap_i64
  89 +//#define TCG_TARGET_HAS_bswap32_i32
  90 +//#define TCG_TARGET_HAS_bswap64_i64
91 91 //#define TCG_TARGET_HAS_neg_i32
92 92 //#define TCG_TARGET_HAS_neg_i64
93 93  
... ...
tcg/tcg-op.h
  View file @66896cb
... ... @@ -1220,10 +1220,10 @@ static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1220 1220 #endif
1221 1221 }
1222 1222  
1223   -static inline void tcg_gen_bswap_i32(TCGv_i32 ret, TCGv_i32 arg)
  1223 +static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1224 1224 {
1225   -#ifdef TCG_TARGET_HAS_bswap_i32
1226   - tcg_gen_op2_i32(INDEX_op_bswap_i32, ret, arg);
  1225 +#ifdef TCG_TARGET_HAS_bswap32_i32
  1226 + tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1227 1227 #else
1228 1228 TCGv_i32 t0, t1;
1229 1229 t0 = tcg_temp_new_i32();
... ... @@ -1300,14 +1300,14 @@ static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1300 1300 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1301 1301 }
1302 1302  
1303   -static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg)
  1303 +static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1304 1304 {
1305 1305 TCGv_i32 t0, t1;
1306 1306 t0 = tcg_temp_new_i32();
1307 1307 t1 = tcg_temp_new_i32();
1308 1308  
1309   - tcg_gen_bswap_i32(t0, TCGV_LOW(arg));
1310   - tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
  1309 + tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
  1310 + tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1311 1311 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1312 1312 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1313 1313 tcg_temp_free_i32(t0);
... ... @@ -1381,10 +1381,10 @@ static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1381 1381 tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1382 1382 }
1383 1383  
1384   -static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg)
  1384 +static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1385 1385 {
1386   -#ifdef TCG_TARGET_HAS_bswap_i64
1387   - tcg_gen_op2_i64(INDEX_op_bswap_i64, ret, arg);
  1386 +#ifdef TCG_TARGET_HAS_bswap64_i64
  1387 + tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1388 1388 #else
1389 1389 TCGv_i32 t0, t1;
1390 1390 t0 = tcg_temp_new_i32();
... ...
tcg/tcg-opc.h
  View file @66896cb
... ... @@ -89,8 +89,8 @@ DEF2(ext8s_i32, 1, 1, 0, 0)
89 89 #ifdef TCG_TARGET_HAS_ext16s_i32
90 90 DEF2(ext16s_i32, 1, 1, 0, 0)
91 91 #endif
92   -#ifdef TCG_TARGET_HAS_bswap_i32
93   -DEF2(bswap_i32, 1, 1, 0, 0)
  92 +#ifdef TCG_TARGET_HAS_bswap32_i32
  93 +DEF2(bswap32_i32, 1, 1, 0, 0)
94 94 #endif
95 95 #ifdef TCG_TARGET_HAS_not_i32
96 96 DEF2(not_i32, 1, 1, 0, 0)
... ... @@ -149,8 +149,8 @@ DEF2(ext16s_i64, 1, 1, 0, 0)
149 149 #ifdef TCG_TARGET_HAS_ext32s_i64
150 150 DEF2(ext32s_i64, 1, 1, 0, 0)
151 151 #endif
152   -#ifdef TCG_TARGET_HAS_bswap_i64
153   -DEF2(bswap_i64, 1, 1, 0, 0)
  152 +#ifdef TCG_TARGET_HAS_bswap64_i64
  153 +DEF2(bswap64_i64, 1, 1, 0, 0)
154 154 #endif
155 155 #ifdef TCG_TARGET_HAS_not_i64
156 156 DEF2(not_i64, 1, 1, 0, 0)
... ...
tcg/x86_64/tcg-target.c
  View file @66896cb
... ... @@ -1094,10 +1094,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1094 1094 args[3], P_REXW);
1095 1095 break;
1096 1096  
1097   - case INDEX_op_bswap_i32:
  1097 + case INDEX_op_bswap32_i32:
1098 1098 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1099 1099 break;
1100   - case INDEX_op_bswap_i64:
  1100 + case INDEX_op_bswap64_i64:
1101 1101 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
1102 1102 break;
1103 1103  
... ... @@ -1287,8 +1287,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
1287 1287  
1288 1288 { INDEX_op_brcond_i64, { "r", "re" } },
1289 1289  
1290   - { INDEX_op_bswap_i32, { "r", "0" } },
1291   - { INDEX_op_bswap_i64, { "r", "0" } },
  1290 + { INDEX_op_bswap32_i32, { "r", "0" } },
  1291 + { INDEX_op_bswap64_i64, { "r", "0" } },
1292 1292  
1293 1293 { INDEX_op_neg_i32, { "r", "0" } },
1294 1294 { INDEX_op_neg_i64, { "r", "0" } },
... ...
tcg/x86_64/tcg-target.h
  View file @66896cb
... ... @@ -56,8 +56,8 @@ enum {
56 56 #define TCG_TARGET_CALL_STACK_OFFSET 0
57 57  
58 58 /* optional instructions */
59   -#define TCG_TARGET_HAS_bswap_i32
60   -#define TCG_TARGET_HAS_bswap_i64
  59 +#define TCG_TARGET_HAS_bswap32_i32
  60 +#define TCG_TARGET_HAS_bswap64_i64
61 61 #define TCG_TARGET_HAS_neg_i32
62 62 #define TCG_TARGET_HAS_neg_i64
63 63 #define TCG_TARGET_HAS_not_i32
... ...