Commit 666713c0711abbc591a867b5ff31fbc6ba53bf28
1 parent
a350db85
Sparc32: refactor CPU init
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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1 changed file
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30 additions
and
45 deletions
hw/sun4m.c
| ... | ... | @@ -530,14 +530,37 @@ static void ram_register_devices(void) |
| 530 | 530 | |
| 531 | 531 | device_init(ram_register_devices); |
| 532 | 532 | |
| 533 | +static CPUState *cpu_devinit(const char *cpu_model, unsigned int id, | |
| 534 | + uint64_t prom_addr, qemu_irq **cpu_irqs) | |
| 535 | +{ | |
| 536 | + CPUState *env; | |
| 537 | + | |
| 538 | + env = cpu_init(cpu_model); | |
| 539 | + if (!env) { | |
| 540 | + fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); | |
| 541 | + exit(1); | |
| 542 | + } | |
| 543 | + | |
| 544 | + cpu_sparc_set_id(env, id); | |
| 545 | + if (id == 0) { | |
| 546 | + qemu_register_reset(main_cpu_reset, env); | |
| 547 | + } else { | |
| 548 | + qemu_register_reset(secondary_cpu_reset, env); | |
| 549 | + env->halted = 1; | |
| 550 | + } | |
| 551 | + *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
| 552 | + env->prom_addr = prom_addr; | |
| 553 | + | |
| 554 | + return env; | |
| 555 | +} | |
| 556 | + | |
| 533 | 557 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
| 534 | 558 | const char *boot_device, |
| 535 | 559 | const char *kernel_filename, |
| 536 | 560 | const char *kernel_cmdline, |
| 537 | 561 | const char *initrd_filename, const char *cpu_model) |
| 538 | - | |
| 539 | 562 | { |
| 540 | - CPUState *env, *envs[MAX_CPUS]; | |
| 563 | + CPUState *envs[MAX_CPUS]; | |
| 541 | 564 | unsigned int i; |
| 542 | 565 | void *iommu, *espdma, *ledma, *nvram; |
| 543 | 566 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
| ... | ... | @@ -555,21 +578,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
| 555 | 578 | cpu_model = hwdef->default_cpu_model; |
| 556 | 579 | |
| 557 | 580 | for(i = 0; i < smp_cpus; i++) { |
| 558 | - env = cpu_init(cpu_model); | |
| 559 | - if (!env) { | |
| 560 | - fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); | |
| 561 | - exit(1); | |
| 562 | - } | |
| 563 | - cpu_sparc_set_id(env, i); | |
| 564 | - envs[i] = env; | |
| 565 | - if (i == 0) { | |
| 566 | - qemu_register_reset(main_cpu_reset, env); | |
| 567 | - } else { | |
| 568 | - qemu_register_reset(secondary_cpu_reset, env); | |
| 569 | - env->halted = 1; | |
| 570 | - } | |
| 571 | - cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); | |
| 572 | - env->prom_addr = hwdef->slavio_base; | |
| 581 | + envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); | |
| 573 | 582 | } |
| 574 | 583 | |
| 575 | 584 | for (i = smp_cpus; i < MAX_CPUS; i++) |
| ... | ... | @@ -1293,7 +1302,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
| 1293 | 1302 | const char *kernel_cmdline, |
| 1294 | 1303 | const char *initrd_filename, const char *cpu_model) |
| 1295 | 1304 | { |
| 1296 | - CPUState *env, *envs[MAX_CPUS]; | |
| 1305 | + CPUState *envs[MAX_CPUS]; | |
| 1297 | 1306 | unsigned int i; |
| 1298 | 1307 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi; |
| 1299 | 1308 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
| ... | ... | @@ -1306,22 +1315,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
| 1306 | 1315 | if (!cpu_model) |
| 1307 | 1316 | cpu_model = hwdef->default_cpu_model; |
| 1308 | 1317 | |
| 1309 | - for (i = 0; i < smp_cpus; i++) { | |
| 1310 | - env = cpu_init(cpu_model); | |
| 1311 | - if (!env) { | |
| 1312 | - fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); | |
| 1313 | - exit(1); | |
| 1314 | - } | |
| 1315 | - cpu_sparc_set_id(env, i); | |
| 1316 | - envs[i] = env; | |
| 1317 | - if (i == 0) { | |
| 1318 | - qemu_register_reset(main_cpu_reset, env); | |
| 1319 | - } else { | |
| 1320 | - qemu_register_reset(secondary_cpu_reset, env); | |
| 1321 | - env->halted = 1; | |
| 1322 | - } | |
| 1323 | - cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); | |
| 1324 | - env->prom_addr = hwdef->slavio_base; | |
| 1318 | + for(i = 0; i < smp_cpus; i++) { | |
| 1319 | + envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); | |
| 1325 | 1320 | } |
| 1326 | 1321 | |
| 1327 | 1322 | for (i = smp_cpus; i < MAX_CPUS; i++) |
| ... | ... | @@ -1493,17 +1488,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
| 1493 | 1488 | if (!cpu_model) |
| 1494 | 1489 | cpu_model = hwdef->default_cpu_model; |
| 1495 | 1490 | |
| 1496 | - env = cpu_init(cpu_model); | |
| 1497 | - if (!env) { | |
| 1498 | - fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); | |
| 1499 | - exit(1); | |
| 1500 | - } | |
| 1501 | - | |
| 1502 | - cpu_sparc_set_id(env, 0); | |
| 1503 | - | |
| 1504 | - qemu_register_reset(main_cpu_reset, env); | |
| 1505 | - cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
| 1506 | - env->prom_addr = hwdef->slavio_base; | |
| 1491 | + env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs); | |
| 1507 | 1492 | |
| 1508 | 1493 | /* set up devices */ |
| 1509 | 1494 | ram_init(0, RAM_size, hwdef->max_mem); | ... | ... |