Commit 653ccb8099e0f87960dc363bf2d875edf0676e8b
1 parent
b5fc09ae
Avoid some brconds
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4318 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
1 changed file
with
12 additions
and
24 deletions
target-sparc/translate.c
| @@ -379,9 +379,6 @@ static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) | @@ -379,9 +379,6 @@ static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) | ||
| 379 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) | 379 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
| 380 | { | 380 | { |
| 381 | TCGv r_temp; | 381 | TCGv r_temp; |
| 382 | - int l1; | ||
| 383 | - | ||
| 384 | - l1 = gen_new_label(); | ||
| 385 | 382 | ||
| 386 | r_temp = tcg_temp_new(TCG_TYPE_TL); | 383 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
| 387 | tcg_gen_xor_tl(r_temp, src1, src2); | 384 | tcg_gen_xor_tl(r_temp, src1, src2); |
| @@ -389,18 +386,15 @@ static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) | @@ -389,18 +386,15 @@ static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) | ||
| 389 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | 386 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| 390 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | 387 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| 391 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | 388 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
| 392 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | ||
| 393 | - tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); | ||
| 394 | - gen_set_label(l1); | 389 | + tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
| 390 | + tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | ||
| 391 | + tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); | ||
| 395 | } | 392 | } |
| 396 | 393 | ||
| 397 | #ifdef TARGET_SPARC64 | 394 | #ifdef TARGET_SPARC64 |
| 398 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) | 395 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
| 399 | { | 396 | { |
| 400 | TCGv r_temp; | 397 | TCGv r_temp; |
| 401 | - int l1; | ||
| 402 | - | ||
| 403 | - l1 = gen_new_label(); | ||
| 404 | 398 | ||
| 405 | r_temp = tcg_temp_new(TCG_TYPE_TL); | 399 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
| 406 | tcg_gen_xor_tl(r_temp, src1, src2); | 400 | tcg_gen_xor_tl(r_temp, src1, src2); |
| @@ -408,9 +402,9 @@ static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) | @@ -408,9 +402,9 @@ static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) | ||
| 408 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | 402 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| 409 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | 403 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| 410 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | 404 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
| 411 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | ||
| 412 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | ||
| 413 | - gen_set_label(l1); | 405 | + tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
| 406 | + tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | ||
| 407 | + tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); | ||
| 414 | } | 408 | } |
| 415 | #endif | 409 | #endif |
| 416 | 410 | ||
| @@ -570,36 +564,30 @@ static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) | @@ -570,36 +564,30 @@ static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) | ||
| 570 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) | 564 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
| 571 | { | 565 | { |
| 572 | TCGv r_temp; | 566 | TCGv r_temp; |
| 573 | - int l1; | ||
| 574 | - | ||
| 575 | - l1 = gen_new_label(); | ||
| 576 | 567 | ||
| 577 | r_temp = tcg_temp_new(TCG_TYPE_TL); | 568 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
| 578 | tcg_gen_xor_tl(r_temp, src1, src2); | 569 | tcg_gen_xor_tl(r_temp, src1, src2); |
| 579 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | 570 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| 580 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | 571 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| 581 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); | 572 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
| 582 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | ||
| 583 | - tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); | ||
| 584 | - gen_set_label(l1); | 573 | + tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
| 574 | + tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | ||
| 575 | + tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); | ||
| 585 | } | 576 | } |
| 586 | 577 | ||
| 587 | #ifdef TARGET_SPARC64 | 578 | #ifdef TARGET_SPARC64 |
| 588 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) | 579 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
| 589 | { | 580 | { |
| 590 | TCGv r_temp; | 581 | TCGv r_temp; |
| 591 | - int l1; | ||
| 592 | - | ||
| 593 | - l1 = gen_new_label(); | ||
| 594 | 582 | ||
| 595 | r_temp = tcg_temp_new(TCG_TYPE_TL); | 583 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
| 596 | tcg_gen_xor_tl(r_temp, src1, src2); | 584 | tcg_gen_xor_tl(r_temp, src1, src2); |
| 597 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); | 585 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
| 598 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | 586 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| 599 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | 587 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
| 600 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | ||
| 601 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | ||
| 602 | - gen_set_label(l1); | 588 | + tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
| 589 | + tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); | ||
| 590 | + tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); | ||
| 603 | } | 591 | } |
| 604 | #endif | 592 | #endif |
| 605 | 593 |