gwj / at91sam9263 · Commits

Commit 65262d57382c228ed62b90a94a0968eb0167bb2d

Authored by bellard
1 parent 773b93ee

added PE to static CPU state (avoids flushing translated code when swiching betw… 

…een protected and real mode) - moved memory defs to cpu-all.h


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@504 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 6 additions and 3 deletions
target-i386/cpu.h
  View file @65262d5
@@ -106,6 +106,11 @@ @@ -106,6 +106,11 @@
106 #define HF_SS32_SHIFT 5 106 #define HF_SS32_SHIFT 5
107 /* zero base for DS, ES and SS */ 107 /* zero base for DS, ES and SS */
108 #define HF_ADDSEG_SHIFT 6 108 #define HF_ADDSEG_SHIFT 6
  109 +/* copy of CR0.PE (protected mode) */
  110 +#define HF_PE_SHIFT 7
  111 +#define HF_TF_SHIFT 8 /* must be same as eflags */
  112 +#define HF_IOPL_SHIFT 12 /* must be same as eflags */
  113 +#define HF_VM_SHIFT 17 /* must be same as eflags */
109 114
110 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 115 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
111 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) 116 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
@@ -113,6 +118,7 @@ @@ -113,6 +118,7 @@
113 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 118 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
114 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 119 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
115 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 120 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
  121 +#define HF_PE_MASK (1 << HF_PE_SHIFT)
116 122
117 #define CR0_PE_MASK (1 << 0) 123 #define CR0_PE_MASK (1 << 0)
118 #define CR0_TS_MASK (1 << 3) 124 #define CR0_TS_MASK (1 << 3)
@@ -391,9 +397,6 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info, @@ -391,9 +397,6 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
391 397
392 /* MMU defines */ 398 /* MMU defines */
393 void cpu_x86_init_mmu(CPUX86State *env); 399 void cpu_x86_init_mmu(CPUX86State *env);
394 -extern int phys_ram_size;  
395 -extern int phys_ram_fd;  
396 -extern uint8_t *phys_ram_base;  
397 extern int a20_enabled; 400 extern int a20_enabled;
398 401
399 void cpu_x86_set_a20(CPUX86State *env, int a20_state); 402 void cpu_x86_set_a20(CPUX86State *env, int a20_state);