gwj / at91sam9263 · Commits

Commit 651721b2a55370cf04794d5ce397984c78fc0fec

Authored by aurel32
1 parent 7d515c1d

targe-ppc: optimize mfcr and mtcrf 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 26 additions and 30 deletions
target-ppc/helper.h
  View file @651721b
... ... @@ -30,9 +30,6 @@ DEF_HELPER_1(dcbz_970, void, tl)
30 30 DEF_HELPER_1(icbi, void, tl)
31 31 DEF_HELPER_4(lscbx, tl, tl, i32, i32, i32)
32 32  
33   -DEF_HELPER_0(load_cr, tl)
34   -DEF_HELPER_2(store_cr, void, tl, i32)
35   -
36 33 #if defined(TARGET_PPC64)
37 34 DEF_HELPER_2(mulhd, i64, i64, i64)
38 35 DEF_HELPER_2(mulhdu, i64, i64, i64)
... ...
target-ppc/op_helper.c
  View file @651721b
... ... @@ -54,30 +54,6 @@ void helper_raise_exception (uint32_t exception)
54 54 }
55 55  
56 56 /*****************************************************************************/
57   -/* Registers load and stores */
58   -target_ulong helper_load_cr (void)
59   -{
60   - return (env->crf[0] << 28) |
61   - (env->crf[1] << 24) |
62   - (env->crf[2] << 20) |
63   - (env->crf[3] << 16) |
64   - (env->crf[4] << 12) |
65   - (env->crf[5] << 8) |
66   - (env->crf[6] << 4) |
67   - (env->crf[7] << 0);
68   -}
69   -
70   -void helper_store_cr (target_ulong val, uint32_t mask)
71   -{
72   - int i, sh;
73   -
74   - for (i = 0, sh = 7; i < 8; i++, sh--) {
75   - if (mask & (1 << sh))
76   - env->crf[i] = (val >> (sh * 4)) & 0xFUL;
77   - }
78   -}
79   -
80   -/*****************************************************************************/
81 57 /* SPR accesses */
82 58 void helper_load_dump_spr (uint32_t sprn)
83 59 {
... ...
target-ppc/translate.c
  View file @651721b
... ... @@ -3859,7 +3859,24 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3859 3859 cpu_gpr[rD(ctx->opcode)], crn * 4);
3860 3860 }
3861 3861 } else {
3862   - gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
  3862 + TCGv_i32 t0 = tcg_temp_new_i32();
  3863 + tcg_gen_mov_i32(t0, cpu_crf[0]);
  3864 + tcg_gen_shli_i32(t0, t0, 4);
  3865 + tcg_gen_or_i32(t0, t0, cpu_crf[1]);
  3866 + tcg_gen_shli_i32(t0, t0, 4);
  3867 + tcg_gen_or_i32(t0, t0, cpu_crf[2]);
  3868 + tcg_gen_shli_i32(t0, t0, 4);
  3869 + tcg_gen_or_i32(t0, t0, cpu_crf[3]);
  3870 + tcg_gen_shli_i32(t0, t0, 4);
  3871 + tcg_gen_or_i32(t0, t0, cpu_crf[4]);
  3872 + tcg_gen_shli_i32(t0, t0, 4);
  3873 + tcg_gen_or_i32(t0, t0, cpu_crf[5]);
  3874 + tcg_gen_shli_i32(t0, t0, 4);
  3875 + tcg_gen_or_i32(t0, t0, cpu_crf[6]);
  3876 + tcg_gen_shli_i32(t0, t0, 4);
  3877 + tcg_gen_or_i32(t0, t0, cpu_crf[7]);
  3878 + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
  3879 + tcg_temp_free_i32(t0);
3863 3880 }
3864 3881 }
3865 3882  
... ... @@ -3956,8 +3973,14 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3956 3973 tcg_temp_free_i32(temp);
3957 3974 }
3958 3975 } else {
3959   - TCGv_i32 temp = tcg_const_i32(crm);
3960   - gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
  3976 + TCGv_i32 temp = tcg_temp_new_i32();
  3977 + tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
  3978 + for (crn = 0 ; crn < 8 ; crn++) {
  3979 + if (crm & (1 << crn)) {
  3980 + tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
  3981 + tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
  3982 + }
  3983 + }
3961 3984 tcg_temp_free_i32(temp);
3962 3985 }
3963 3986 }
... ...