Commit 647de6ca243aab87a1fa480f3ffe4e64c922bcf2
1 parent
932a79df
Handle IBE on MIPS properly.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3416 c046a42c-6fe2-441c-8c8c-71466251a162
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3 changed files
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12 additions
and
1 deletions
exec-all.h
| ... | ... | @@ -608,7 +608,7 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 608 | 608 | } |
| 609 | 609 | pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; |
| 610 | 610 | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
| 611 | -#ifdef TARGET_SPARC | |
| 611 | +#if defined(TARGET_SPARC) || defined(TARGET_MIPS) | |
| 612 | 612 | do_unassigned_access(addr, 0, 1, 0); |
| 613 | 613 | #else |
| 614 | 614 | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); | ... | ... |
target-mips/cpu.h
| ... | ... | @@ -479,6 +479,9 @@ int mips_find_by_name (const unsigned char *name, mips_def_t **def); |
| 479 | 479 | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 480 | 480 | int cpu_mips_register (CPUMIPSState *env, mips_def_t *def); |
| 481 | 481 | |
| 482 | +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, | |
| 483 | + int unused); | |
| 484 | + | |
| 482 | 485 | #define CPUState CPUMIPSState |
| 483 | 486 | #define cpu_init cpu_mips_init |
| 484 | 487 | #define cpu_exec cpu_mips_exec | ... | ... |
target-mips/op_helper.c
| ... | ... | @@ -591,6 +591,14 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
| 591 | 591 | env = saved_env; |
| 592 | 592 | } |
| 593 | 593 | |
| 594 | +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, | |
| 595 | + int unused) | |
| 596 | +{ | |
| 597 | + if (is_exec) | |
| 598 | + do_raise_exception(EXCP_IBE); | |
| 599 | + else | |
| 600 | + do_raise_exception(EXCP_DBE); | |
| 601 | +} | |
| 594 | 602 | #endif |
| 595 | 603 | |
| 596 | 604 | /* Complex FPU operations which may need stack space. */ | ... | ... |