gwj / at91sam9263 · Commits

Commit 6341fdcb7841f364a6102ce2b3c375e6c0d7560e

Authored by blueswir1
1 parent 37191109

Fix CPU timer interrupts 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3876 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 16 additions and 11 deletions
hw/slavio_intctl.c
  View file @6341fdc
@@ -70,7 +70,8 @@ typedef struct SLAVIO_INTCTLState { @@ -70,7 +70,8 @@ typedef struct SLAVIO_INTCTLState {
70 #define INTCTLM_MASK 0x1f 70 #define INTCTLM_MASK 0x1f
71 #define MASTER_IRQ_MASK ~0x0fa2007f 71 #define MASTER_IRQ_MASK ~0x0fa2007f
72 #define MASTER_DISABLE 0x80000000 72 #define MASTER_DISABLE 0x80000000
73 -#define CPU_IRQ_MASK 0xfffe0000 73 +#define CPU_SOFTIRQ_MASK 0xfffe0000
  74 +#define CPU_HARDIRQ_MASK 0x0000fffe
74 #define CPU_IRQ_INT15_IN 0x0004000 75 #define CPU_IRQ_INT15_IN 0x0004000
75 #define CPU_IRQ_INT15_MASK 0x80000000 76 #define CPU_IRQ_INT15_MASK 0x80000000
76 77
@@ -111,13 +112,13 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint @@ -111,13 +112,13 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
111 case 1: // clear pending softints 112 case 1: // clear pending softints
112 if (val & CPU_IRQ_INT15_IN) 113 if (val & CPU_IRQ_INT15_IN)
113 val |= CPU_IRQ_INT15_MASK; 114 val |= CPU_IRQ_INT15_MASK;
114 - val &= CPU_IRQ_MASK; 115 + val &= CPU_SOFTIRQ_MASK;
115 s->intreg_pending[cpu] &= ~val; 116 s->intreg_pending[cpu] &= ~val;
116 slavio_check_interrupts(s); 117 slavio_check_interrupts(s);
117 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); 118 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
118 break; 119 break;
119 case 2: // set softint 120 case 2: // set softint
120 - val &= CPU_IRQ_MASK; 121 + val &= CPU_SOFTIRQ_MASK;
121 s->intreg_pending[cpu] |= val; 122 s->intreg_pending[cpu] |= val;
122 slavio_check_interrupts(s); 123 slavio_check_interrupts(s);
123 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); 124 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
@@ -256,8 +257,9 @@ static void slavio_check_interrupts(void *opaque) @@ -256,8 +257,9 @@ static void slavio_check_interrupts(void *opaque)
256 if (pending & (1 << j)) 257 if (pending & (1 << j))
257 pil_pending |= 1 << s->intbit_to_level[j]; 258 pil_pending |= 1 << s->intbit_to_level[j];
258 } 259 }
  260 + pil_pending |= s->intreg_pending[i] & CPU_HARDIRQ_MASK;
259 } 261 }
260 - pil_pending |= (s->intreg_pending[i] & CPU_IRQ_MASK) >> 16; 262 + pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
261 263
262 for (j = 0; j < MAX_PILS; j++) { 264 for (j = 0; j < MAX_PILS; j++) {
263 if (pil_pending & (1 << j)) { 265 if (pil_pending & (1 << j)) {
@@ -386,7 +388,7 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, @@ -386,7 +388,7 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
386 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32); 388 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
387 389
388 *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS); 390 *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
389 - s->cputimer_bit = 1 << s->intbit_to_level[cputimer]; 391 + s->cputimer_bit = 1 << cputimer;
390 slavio_intctl_reset(s); 392 slavio_intctl_reset(s);
391 return s; 393 return s;
392 } 394 }
hw/slavio_timer.c
  View file @6341fdc
@@ -253,6 +253,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, @@ -253,6 +253,8 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
253 if (val & (1 << i)) { 253 if (val & (1 << i)) {
254 qemu_irq_lower(s->slave[i]->irq); 254 qemu_irq_lower(s->slave[i]->irq);
255 s->slave[i]->limit = -1ULL; 255 s->slave[i]->limit = -1ULL;
  256 + } else {
  257 + ptimer_stop(s->slave[i]->timer);
256 } 258 }
257 if ((val & (1 << i)) != (s->slave_mode & (1 << i))) { 259 if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
258 ptimer_stop(s->slave[i]->timer); 260 ptimer_stop(s->slave[i]->timer);
hw/sun4m.c
  View file @6341fdc
@@ -88,8 +88,9 @@ struct hwdef { @@ -88,8 +88,9 @@ struct hwdef {
88 uint32_t ecc_version; 88 uint32_t ecc_version;
89 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; 89 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
90 long vram_size, nvram_size; 90 long vram_size, nvram_size;
91 - // IRQ numbers are not PIL ones, but master interrupt controller register  
92 - // bit numbers 91 + // IRQ numbers are not PIL ones, but master interrupt controller
  92 + // register bit numbers except for clock_irq, which indexes cpu
  93 + // interrupt controller register
93 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; 94 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
94 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq; 95 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
95 int machine_id; // For NVRAM 96 int machine_id; // For NVRAM
@@ -691,7 +692,7 @@ static const struct hwdef hwdefs[] = { @@ -691,7 +692,7 @@ static const struct hwdef hwdefs[] = {
691 .nvram_size = 0x2000, 692 .nvram_size = 0x2000,
692 .esp_irq = 18, 693 .esp_irq = 18,
693 .le_irq = 16, 694 .le_irq = 16,
694 - .clock_irq = 7, 695 + .clock_irq = 14,
695 .clock1_irq = 19, 696 .clock1_irq = 19,
696 .ms_kb_irq = 14, 697 .ms_kb_irq = 14,
697 .ser_irq = 15, 698 .ser_irq = 15,
@@ -732,7 +733,7 @@ static const struct hwdef hwdefs[] = { @@ -732,7 +733,7 @@ static const struct hwdef hwdefs[] = {
732 .nvram_size = 0x2000, 733 .nvram_size = 0x2000,
733 .esp_irq = 18, 734 .esp_irq = 18,
734 .le_irq = 16, 735 .le_irq = 16,
735 - .clock_irq = 7, 736 + .clock_irq = 14,
736 .clock1_irq = 19, 737 .clock1_irq = 19,
737 .ms_kb_irq = 14, 738 .ms_kb_irq = 14,
738 .ser_irq = 15, 739 .ser_irq = 15,
@@ -773,7 +774,7 @@ static const struct hwdef hwdefs[] = { @@ -773,7 +774,7 @@ static const struct hwdef hwdefs[] = {
773 .nvram_size = 0x2000, 774 .nvram_size = 0x2000,
774 .esp_irq = 18, 775 .esp_irq = 18,
775 .le_irq = 16, 776 .le_irq = 16,
776 - .clock_irq = 7, 777 + .clock_irq = 14,
777 .clock1_irq = 19, 778 .clock1_irq = 19,
778 .ms_kb_irq = 14, 779 .ms_kb_irq = 14,
779 .ser_irq = 15, 780 .ser_irq = 15,
@@ -814,7 +815,7 @@ static const struct hwdef hwdefs[] = { @@ -814,7 +815,7 @@ static const struct hwdef hwdefs[] = {
814 .nvram_size = 0x2000, 815 .nvram_size = 0x2000,
815 .esp_irq = 18, 816 .esp_irq = 18,
816 .le_irq = 16, 817 .le_irq = 16,
817 - .clock_irq = 7, 818 + .clock_irq = 14,
818 .clock1_irq = 19, 819 .clock1_irq = 19,
819 .ms_kb_irq = 14, 820 .ms_kb_irq = 14,
820 .ser_irq = 15, 821 .ser_irq = 15,