gwj / at91sam9263 · Commits

Commit 62c5609aa537a9c7f3c70e4baa5e67060368baa3

Authored by ths
1 parent 97428a4d

Catch unaligned sc/scd. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2642 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 10 additions and 0 deletions
target-mips/op_mem.c
  View file @62c5609
@@ -117,6 +117,10 @@ void glue(op_ll, MEMSUFFIX) (void) @@ -117,6 +117,10 @@ void glue(op_ll, MEMSUFFIX) (void)
117 void glue(op_sc, MEMSUFFIX) (void) 117 void glue(op_sc, MEMSUFFIX) (void)
118 { 118 {
119 CALL_FROM_TB0(dump_sc); 119 CALL_FROM_TB0(dump_sc);
  120 + if (T0 & 0x3) {
  121 + env->CP0_BadVAddr = T0;
  122 + CALL_FROM_TB1(do_raise_exception, EXCP_AdES);
  123 + }
120 if (T0 == env->CP0_LLAddr) { 124 if (T0 == env->CP0_LLAddr) {
121 glue(stl, MEMSUFFIX)(T0, T1); 125 glue(stl, MEMSUFFIX)(T0, T1);
122 T0 = 1; 126 T0 = 1;
@@ -182,6 +186,10 @@ void glue(op_lld, MEMSUFFIX) (void) @@ -182,6 +186,10 @@ void glue(op_lld, MEMSUFFIX) (void)
182 void glue(op_scd, MEMSUFFIX) (void) 186 void glue(op_scd, MEMSUFFIX) (void)
183 { 187 {
184 CALL_FROM_TB0(dump_sc); 188 CALL_FROM_TB0(dump_sc);
  189 + if (T0 & 0x7) {
  190 + env->CP0_BadVAddr = T0;
  191 + CALL_FROM_TB1(do_raise_exception, EXCP_AdES);
  192 + }
185 if (T0 == env->CP0_LLAddr) { 193 if (T0 == env->CP0_LLAddr) {
186 glue(stq, MEMSUFFIX)(T0, T1); 194 glue(stq, MEMSUFFIX)(T0, T1);
187 T0 = 1; 195 T0 = 1;
target-mips/translate.c
  View file @62c5609
@@ -714,6 +714,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, @@ -714,6 +714,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
714 opn = "sd"; 714 opn = "sd";
715 break; 715 break;
716 case OPC_SCD: 716 case OPC_SCD:
  717 + save_cpu_state(ctx, 1);
717 GEN_LOAD_REG_TN(T1, rt); 718 GEN_LOAD_REG_TN(T1, rt);
718 op_ldst(scd); 719 op_ldst(scd);
719 opn = "scd"; 720 opn = "scd";
@@ -812,6 +813,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, @@ -812,6 +813,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
812 opn = "ll"; 813 opn = "ll";
813 break; 814 break;
814 case OPC_SC: 815 case OPC_SC:
  816 + save_cpu_state(ctx, 1);
815 GEN_LOAD_REG_TN(T1, rt); 817 GEN_LOAD_REG_TN(T1, rt);
816 op_ldst(sc); 818 op_ldst(sc);
817 GEN_STORE_TN_REG(rt, T0); 819 GEN_STORE_TN_REG(rt, T0);