gwj / at91sam9263 · Commits

Commit 610c3c8afd99f4f118b12ede39ee8d62ee44a446

Authored by balrog
1 parent b6d7c3db

Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3013 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 20 additions and 4 deletions
target-arm/cpu.h
  View file @610c3c8
... ... @@ -83,6 +83,7 @@ typedef struct CPUARMState {
83 83 uint32_t c0_cachetype;
84 84 uint32_t c1_sys; /* System control register. */
85 85 uint32_t c1_coproc; /* Coprocessor access register. */
  86 + uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
86 87 uint32_t c2_base; /* MMU translation table base. */
87 88 uint32_t c2_data; /* MPU data cachable bits. */
88 89 uint32_t c2_insn; /* MPU instruction cachable bits. */
... ...
target-arm/helper.c
  View file @610c3c8
... ... @@ -18,16 +18,19 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
18 18 set_feature(env, ARM_FEATURE_VFP);
19 19 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
20 20 env->cp15.c0_cachetype = 0x1dd20d2;
  21 + env->cp15.c1_sys = 0x00090078;
21 22 break;
22 23 case ARM_CPUID_ARM946:
23 24 set_feature(env, ARM_FEATURE_MPU);
24 25 env->cp15.c0_cachetype = 0x0f004006;
  26 + env->cp15.c1_sys = 0x00000078;
25 27 break;
26 28 case ARM_CPUID_ARM1026:
27 29 set_feature(env, ARM_FEATURE_VFP);
28 30 set_feature(env, ARM_FEATURE_AUXCR);
29 31 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
30 32 env->cp15.c0_cachetype = 0x1dd20d2;
  33 + env->cp15.c1_sys = 0x00090078;
31 34 break;
32 35 case ARM_CPUID_PXA250:
33 36 case ARM_CPUID_PXA255:
... ... @@ -37,6 +40,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
37 40 set_feature(env, ARM_FEATURE_XSCALE);
38 41 /* JTAG_ID is ((id << 28) | 0x09265013) */
39 42 env->cp15.c0_cachetype = 0xd172172;
  43 + env->cp15.c1_sys = 0x00000078;
40 44 break;
41 45 case ARM_CPUID_PXA270_A0:
42 46 case ARM_CPUID_PXA270_A1:
... ... @@ -49,6 +53,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
49 53 set_feature(env, ARM_FEATURE_IWMMXT);
50 54 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
51 55 env->cp15.c0_cachetype = 0xd172172;
  56 + env->cp15.c1_sys = 0x00000078;
52 57 break;
53 58 default:
54 59 cpu_abort(env, "Bad CPU ID: %x\n", id);
... ... @@ -637,6 +642,8 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
637 642 crm = insn & 0xf;
638 643 switch ((insn >> 16) & 0xf) {
639 644 case 0: /* ID codes. */
  645 + if (arm_feature(env, ARM_FEATURE_XSCALE))
  646 + break;
640 647 goto bad_reg;
641 648 case 1: /* System configuration. */
642 649 switch (op2) {
... ... @@ -648,12 +655,14 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
648 655 tlb_flush(env, 1);
649 656 break;
650 657 case 1:
651   - /* XScale doesn't implement AUX CR (P-Bit) but allows
652   - * writing with zero and reading. */
653   - if (arm_feature(env, ARM_FEATURE_XSCALE))
  658 + if (arm_feature(env, ARM_FEATURE_XSCALE)) {
  659 + env->cp15.c1_xscaleauxcr = val;
654 660 break;
  661 + }
655 662 goto bad_reg;
656 663 case 2:
  664 + if (arm_feature(env, ARM_FEATURE_XSCALE))
  665 + goto bad_reg;
657 666 env->cp15.c1_coproc = val;
658 667 /* ??? Is this safe when called from within a TB? */
659 668 tb_flush(env);
... ... @@ -835,6 +844,8 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
835 844 case 1: /* Cache Type. */
836 845 return env->cp15.c0_cachetype;
837 846 case 2: /* TCM status. */
  847 + if (arm_feature(env, ARM_FEATURE_XSCALE))
  848 + goto bad_reg;
838 849 return 0;
839 850 }
840 851 case 1: /* System configuration. */
... ... @@ -845,9 +856,11 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
845 856 if (arm_feature(env, ARM_FEATURE_AUXCR))
846 857 return 1;
847 858 if (arm_feature(env, ARM_FEATURE_XSCALE))
848   - return 0;
  859 + return env->cp15.c1_xscaleauxcr;
849 860 goto bad_reg;
850 861 case 2: /* Coprocessor access register. */
  862 + if (arm_feature(env, ARM_FEATURE_XSCALE))
  863 + goto bad_reg;
851 864 return env->cp15.c1_coproc;
852 865 default:
853 866 goto bad_reg;
... ...
... ... @@ -5717,6 +5717,7 @@ void cpu_save(QEMUFile *f, void *opaque)
5717 5717 qemu_put_be32(f, env->cp15.c0_cachetype);
5718 5718 qemu_put_be32(f, env->cp15.c1_sys);
5719 5719 qemu_put_be32(f, env->cp15.c1_coproc);
  5720 + qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
5720 5721 qemu_put_be32(f, env->cp15.c2_base);
5721 5722 qemu_put_be32(f, env->cp15.c2_data);
5722 5723 qemu_put_be32(f, env->cp15.c2_insn);
... ... @@ -5788,6 +5789,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
5788 5789 env->cp15.c0_cachetype = qemu_get_be32(f);
5789 5790 env->cp15.c1_sys = qemu_get_be32(f);
5790 5791 env->cp15.c1_coproc = qemu_get_be32(f);
  5792 + env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
5791 5793 env->cp15.c2_base = qemu_get_be32(f);
5792 5794 env->cp15.c2_data = qemu_get_be32(f);
5793 5795 env->cp15.c2_insn = qemu_get_be32(f);
... ...