gwj / at91sam9263 · Commits

Commit 601d70b9e5dea95a3854ba801672786f40230b75

Authored by balrog
1 parent 66230e0d

Remove an unused field and fix some non-code typos. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 5 additions and 6 deletions
hw/twl92230.c
  View file @601d70b
... ... @@ -62,7 +62,6 @@ struct menelaus_s {
62 62 int sec_offset;
63 63 int alm_sec;
64 64 int next_comp;
65   - struct tm *(*gettime)(const time_t *timep, struct tm *result);
66 65 } rtc;
67 66 qemu_irq handler[3];
68 67 qemu_irq *in;
... ...
target-arm/helper.c
  View file @601d70b
... ... @@ -737,7 +737,7 @@ void do_interrupt(CPUARMState *env)
737 737 new_mode = ARM_CPU_MODE_SVC;
738 738 addr = 0x08;
739 739 mask = CPSR_I;
740   - /* The PC already points to the next instructon. */
  740 + /* The PC already points to the next instruction. */
741 741 offset = 0;
742 742 break;
743 743 case EXCP_BKPT:
... ... @@ -870,7 +870,7 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
870 870 type = (desc & 3);
871 871 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
872 872 if (type == 0) {
873   - /* Secton translation fault. */
  873 + /* Section translation fault. */
874 874 code = 5;
875 875 goto do_fault;
876 876 }
... ... @@ -961,7 +961,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
961 961 desc = ldl_phys(table);
962 962 type = (desc & 3);
963 963 if (type == 0) {
964   - /* Secton translation fault. */
  964 + /* Section translation fault. */
965 965 code = 5;
966 966 domain = 0;
967 967 goto do_fault;
... ...
target-arm/translate.c
  View file @601d70b
... ... @@ -2877,7 +2877,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2877 2877 tmp = load_cpu_field(vfp.xregs[rn]);
2878 2878 break;
2879 2879 case ARM_VFP_FPSCR:
2880   - if (rd == 15) {
  2880 + if (rd == 15) {
2881 2881 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2882 2882 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2883 2883 } else {
... ... @@ -6887,7 +6887,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
6887 6887  
6888 6888 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
6889 6889 || arm_feature (env, ARM_FEATURE_M))) {
6890   - /* Thumb-1 cores may need to tread bl and blx as a pair of
  6890 + /* Thumb-1 cores may need to treat bl and blx as a pair of
6891 6891 16-bit instructions to get correct prefetch abort behavior. */
6892 6892 insn = insn_hw1;
6893 6893 if ((insn & (1 << 12)) == 0) {
... ...