Commit 5ef62c5c4224afdce2f98fb2c3b43f734ab47f72
1 parent
32af58f9
More Sparc32 CPUs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2744 c046a42c-6fe2-441c-8c8c-71466251a162
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20 additions
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3 deletions
target-sparc/translate.c
| @@ -3355,11 +3355,28 @@ static const sparc_def_t sparc_defs[] = { | @@ -3355,11 +3355,28 @@ static const sparc_def_t sparc_defs[] = { | ||
| 3355 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ | 3355 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
| 3356 | }, | 3356 | }, |
| 3357 | { | 3357 | { |
| 3358 | - /* XXX: Replace with real values */ | 3358 | + .name = "Fujitsu MB86907", |
| 3359 | + .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ | ||
| 3360 | + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ | ||
| 3361 | + .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ | ||
| 3362 | + }, | ||
| 3363 | + { | ||
| 3364 | + .name = "TI MicroSparc I", | ||
| 3365 | + .iu_version = 0x41000000, | ||
| 3366 | + .fpu_version = 4 << 17, | ||
| 3367 | + .mmu_version = 0x41000000, | ||
| 3368 | + }, | ||
| 3369 | + { | ||
| 3359 | .name = "TI SuperSparc II", | 3370 | .name = "TI SuperSparc II", |
| 3360 | .iu_version = 0x40000000, | 3371 | .iu_version = 0x40000000, |
| 3361 | - .fpu_version = 0x00000000, | ||
| 3362 | - .mmu_version = 0x00000000, | 3372 | + .fpu_version = 0 << 17, |
| 3373 | + .mmu_version = 0x04000000, | ||
| 3374 | + }, | ||
| 3375 | + { | ||
| 3376 | + .name = "Ross RT620", | ||
| 3377 | + .iu_version = 0x1e000000, | ||
| 3378 | + .fpu_version = 1 << 17, | ||
| 3379 | + .mmu_version = 0x17000000, | ||
| 3363 | }, | 3380 | }, |
| 3364 | #endif | 3381 | #endif |
| 3365 | }; | 3382 | }; |