Commit 5d0fc900d35e9f272c79d199e5854be8301dccf3
1 parent
0d1d0094
Call most FP helpers without deroute through op.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4734 c046a42c-6fe2-441c-8c8c-71466251a162
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4 changed files
with
154 additions
and
364 deletions
target-mips/exec.h
| @@ -103,79 +103,6 @@ void cpu_mips_update_irq (CPUState *env); | @@ -103,79 +103,6 @@ void cpu_mips_update_irq (CPUState *env); | ||
| 103 | void cpu_mips_clock_init (CPUState *env); | 103 | void cpu_mips_clock_init (CPUState *env); |
| 104 | void cpu_mips_tlb_flush (CPUState *env, int flush_global); | 104 | void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
| 105 | 105 | ||
| 106 | -#define FOP_PROTO(op) \ | ||
| 107 | -void do_float_ ## op ## _s(void); \ | ||
| 108 | -void do_float_ ## op ## _d(void); | ||
| 109 | -FOP_PROTO(roundl) | ||
| 110 | -FOP_PROTO(roundw) | ||
| 111 | -FOP_PROTO(truncl) | ||
| 112 | -FOP_PROTO(truncw) | ||
| 113 | -FOP_PROTO(ceill) | ||
| 114 | -FOP_PROTO(ceilw) | ||
| 115 | -FOP_PROTO(floorl) | ||
| 116 | -FOP_PROTO(floorw) | ||
| 117 | -FOP_PROTO(rsqrt) | ||
| 118 | -FOP_PROTO(recip) | ||
| 119 | -#undef FOP_PROTO | ||
| 120 | - | ||
| 121 | -#define FOP_PROTO(op) \ | ||
| 122 | -void do_float_ ## op ## _s(void); \ | ||
| 123 | -void do_float_ ## op ## _d(void); \ | ||
| 124 | -void do_float_ ## op ## _ps(void); | ||
| 125 | -FOP_PROTO(add) | ||
| 126 | -FOP_PROTO(sub) | ||
| 127 | -FOP_PROTO(mul) | ||
| 128 | -FOP_PROTO(div) | ||
| 129 | -FOP_PROTO(recip1) | ||
| 130 | -FOP_PROTO(recip2) | ||
| 131 | -FOP_PROTO(rsqrt1) | ||
| 132 | -FOP_PROTO(rsqrt2) | ||
| 133 | -#undef FOP_PROTO | ||
| 134 | - | ||
| 135 | -void do_float_cvtd_s(void); | ||
| 136 | -void do_float_cvtd_w(void); | ||
| 137 | -void do_float_cvtd_l(void); | ||
| 138 | -void do_float_cvtl_d(void); | ||
| 139 | -void do_float_cvtl_s(void); | ||
| 140 | -void do_float_cvtps_pw(void); | ||
| 141 | -void do_float_cvtpw_ps(void); | ||
| 142 | -void do_float_cvts_d(void); | ||
| 143 | -void do_float_cvts_w(void); | ||
| 144 | -void do_float_cvts_l(void); | ||
| 145 | -void do_float_cvts_pl(void); | ||
| 146 | -void do_float_cvts_pu(void); | ||
| 147 | -void do_float_cvtw_s(void); | ||
| 148 | -void do_float_cvtw_d(void); | ||
| 149 | - | ||
| 150 | -void do_float_addr_ps(void); | ||
| 151 | -void do_float_mulr_ps(void); | ||
| 152 | - | ||
| 153 | -#define FOP_PROTO(op) \ | ||
| 154 | -void do_cmp_d_ ## op(long cc); \ | ||
| 155 | -void do_cmpabs_d_ ## op(long cc); \ | ||
| 156 | -void do_cmp_s_ ## op(long cc); \ | ||
| 157 | -void do_cmpabs_s_ ## op(long cc); \ | ||
| 158 | -void do_cmp_ps_ ## op(long cc); \ | ||
| 159 | -void do_cmpabs_ps_ ## op(long cc); | ||
| 160 | - | ||
| 161 | -FOP_PROTO(f) | ||
| 162 | -FOP_PROTO(un) | ||
| 163 | -FOP_PROTO(eq) | ||
| 164 | -FOP_PROTO(ueq) | ||
| 165 | -FOP_PROTO(olt) | ||
| 166 | -FOP_PROTO(ult) | ||
| 167 | -FOP_PROTO(ole) | ||
| 168 | -FOP_PROTO(ule) | ||
| 169 | -FOP_PROTO(sf) | ||
| 170 | -FOP_PROTO(ngle) | ||
| 171 | -FOP_PROTO(seq) | ||
| 172 | -FOP_PROTO(ngl) | ||
| 173 | -FOP_PROTO(lt) | ||
| 174 | -FOP_PROTO(nge) | ||
| 175 | -FOP_PROTO(le) | ||
| 176 | -FOP_PROTO(ngt) | ||
| 177 | -#undef FOP_PROTO | ||
| 178 | - | ||
| 179 | static always_inline void env_to_regs(void) | 106 | static always_inline void env_to_regs(void) |
| 180 | { | 107 | { |
| 181 | } | 108 | } |
target-mips/helper.h
| @@ -130,3 +130,75 @@ DEF_HELPER(void, do_yield, (void)) | @@ -130,3 +130,75 @@ DEF_HELPER(void, do_yield, (void)) | ||
| 130 | /* CP1 functions */ | 130 | /* CP1 functions */ |
| 131 | DEF_HELPER(void, do_cfc1, (uint32_t reg)) | 131 | DEF_HELPER(void, do_cfc1, (uint32_t reg)) |
| 132 | DEF_HELPER(void, do_ctc1, (uint32_t reg)) | 132 | DEF_HELPER(void, do_ctc1, (uint32_t reg)) |
| 133 | + | ||
| 134 | +DEF_HELPER(void, do_float_cvtd_s, (void)) | ||
| 135 | +DEF_HELPER(void, do_float_cvtd_w, (void)) | ||
| 136 | +DEF_HELPER(void, do_float_cvtd_l, (void)) | ||
| 137 | +DEF_HELPER(void, do_float_cvtl_d, (void)) | ||
| 138 | +DEF_HELPER(void, do_float_cvtl_s, (void)) | ||
| 139 | +DEF_HELPER(void, do_float_cvtps_pw, (void)) | ||
| 140 | +DEF_HELPER(void, do_float_cvtpw_ps, (void)) | ||
| 141 | +DEF_HELPER(void, do_float_cvts_d, (void)) | ||
| 142 | +DEF_HELPER(void, do_float_cvts_w, (void)) | ||
| 143 | +DEF_HELPER(void, do_float_cvts_l, (void)) | ||
| 144 | +DEF_HELPER(void, do_float_cvts_pl, (void)) | ||
| 145 | +DEF_HELPER(void, do_float_cvts_pu, (void)) | ||
| 146 | +DEF_HELPER(void, do_float_cvtw_s, (void)) | ||
| 147 | +DEF_HELPER(void, do_float_cvtw_d, (void)) | ||
| 148 | + | ||
| 149 | +DEF_HELPER(void, do_float_addr_ps, (void)) | ||
| 150 | +DEF_HELPER(void, do_float_mulr_ps, (void)) | ||
| 151 | + | ||
| 152 | +#define FOP_PROTO(op) \ | ||
| 153 | +DEF_HELPER(void, do_float_ ## op ## _s, (void)) \ | ||
| 154 | +DEF_HELPER(void, do_float_ ## op ## _d, (void)) | ||
| 155 | +FOP_PROTO(roundl) | ||
| 156 | +FOP_PROTO(roundw) | ||
| 157 | +FOP_PROTO(truncl) | ||
| 158 | +FOP_PROTO(truncw) | ||
| 159 | +FOP_PROTO(ceill) | ||
| 160 | +FOP_PROTO(ceilw) | ||
| 161 | +FOP_PROTO(floorl) | ||
| 162 | +FOP_PROTO(floorw) | ||
| 163 | +FOP_PROTO(rsqrt) | ||
| 164 | +FOP_PROTO(recip) | ||
| 165 | +#undef FOP_PROTO | ||
| 166 | + | ||
| 167 | +#define FOP_PROTO(op) \ | ||
| 168 | +DEF_HELPER(void, do_float_ ## op ## _s, (void)) \ | ||
| 169 | +DEF_HELPER(void, do_float_ ## op ## _d, (void)) \ | ||
| 170 | +DEF_HELPER(void, do_float_ ## op ## _ps, (void)) | ||
| 171 | +FOP_PROTO(add) | ||
| 172 | +FOP_PROTO(sub) | ||
| 173 | +FOP_PROTO(mul) | ||
| 174 | +FOP_PROTO(div) | ||
| 175 | +FOP_PROTO(recip1) | ||
| 176 | +FOP_PROTO(recip2) | ||
| 177 | +FOP_PROTO(rsqrt1) | ||
| 178 | +FOP_PROTO(rsqrt2) | ||
| 179 | +#undef FOP_PROTO | ||
| 180 | + | ||
| 181 | +#define FOP_PROTO(op) \ | ||
| 182 | +DEF_HELPER(void, do_cmp_d_ ## op, (long cc)) \ | ||
| 183 | +DEF_HELPER(void, do_cmpabs_d_ ## op, (long cc)) \ | ||
| 184 | +DEF_HELPER(void, do_cmp_s_ ## op, (long cc)) \ | ||
| 185 | +DEF_HELPER(void, do_cmpabs_s_ ## op, (long cc)) \ | ||
| 186 | +DEF_HELPER(void, do_cmp_ps_ ## op, (long cc)) \ | ||
| 187 | +DEF_HELPER(void, do_cmpabs_ps_ ## op, (long cc)) | ||
| 188 | +FOP_PROTO(f) | ||
| 189 | +FOP_PROTO(un) | ||
| 190 | +FOP_PROTO(eq) | ||
| 191 | +FOP_PROTO(ueq) | ||
| 192 | +FOP_PROTO(olt) | ||
| 193 | +FOP_PROTO(ult) | ||
| 194 | +FOP_PROTO(ole) | ||
| 195 | +FOP_PROTO(ule) | ||
| 196 | +FOP_PROTO(sf) | ||
| 197 | +FOP_PROTO(ngle) | ||
| 198 | +FOP_PROTO(seq) | ||
| 199 | +FOP_PROTO(ngl) | ||
| 200 | +FOP_PROTO(lt) | ||
| 201 | +FOP_PROTO(nge) | ||
| 202 | +FOP_PROTO(le) | ||
| 203 | +FOP_PROTO(ngt) | ||
| 204 | +#undef FOP_PROTO |
target-mips/op.c
| @@ -377,36 +377,6 @@ void op_dmultu (void) | @@ -377,36 +377,6 @@ void op_dmultu (void) | ||
| 377 | 377 | ||
| 378 | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) | 378 | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
| 379 | 379 | ||
| 380 | -FLOAT_OP(cvtd, s) | ||
| 381 | -{ | ||
| 382 | - CALL_FROM_TB0(do_float_cvtd_s); | ||
| 383 | - DEBUG_FPU_STATE(); | ||
| 384 | - FORCE_RET(); | ||
| 385 | -} | ||
| 386 | -FLOAT_OP(cvtd, w) | ||
| 387 | -{ | ||
| 388 | - CALL_FROM_TB0(do_float_cvtd_w); | ||
| 389 | - DEBUG_FPU_STATE(); | ||
| 390 | - FORCE_RET(); | ||
| 391 | -} | ||
| 392 | -FLOAT_OP(cvtd, l) | ||
| 393 | -{ | ||
| 394 | - CALL_FROM_TB0(do_float_cvtd_l); | ||
| 395 | - DEBUG_FPU_STATE(); | ||
| 396 | - FORCE_RET(); | ||
| 397 | -} | ||
| 398 | -FLOAT_OP(cvtl, d) | ||
| 399 | -{ | ||
| 400 | - CALL_FROM_TB0(do_float_cvtl_d); | ||
| 401 | - DEBUG_FPU_STATE(); | ||
| 402 | - FORCE_RET(); | ||
| 403 | -} | ||
| 404 | -FLOAT_OP(cvtl, s) | ||
| 405 | -{ | ||
| 406 | - CALL_FROM_TB0(do_float_cvtl_s); | ||
| 407 | - DEBUG_FPU_STATE(); | ||
| 408 | - FORCE_RET(); | ||
| 409 | -} | ||
| 410 | FLOAT_OP(cvtps, s) | 380 | FLOAT_OP(cvtps, s) |
| 411 | { | 381 | { |
| 412 | WT2 = WT0; | 382 | WT2 = WT0; |
| @@ -414,60 +384,6 @@ FLOAT_OP(cvtps, s) | @@ -414,60 +384,6 @@ FLOAT_OP(cvtps, s) | ||
| 414 | DEBUG_FPU_STATE(); | 384 | DEBUG_FPU_STATE(); |
| 415 | FORCE_RET(); | 385 | FORCE_RET(); |
| 416 | } | 386 | } |
| 417 | -FLOAT_OP(cvtps, pw) | ||
| 418 | -{ | ||
| 419 | - CALL_FROM_TB0(do_float_cvtps_pw); | ||
| 420 | - DEBUG_FPU_STATE(); | ||
| 421 | - FORCE_RET(); | ||
| 422 | -} | ||
| 423 | -FLOAT_OP(cvtpw, ps) | ||
| 424 | -{ | ||
| 425 | - CALL_FROM_TB0(do_float_cvtpw_ps); | ||
| 426 | - DEBUG_FPU_STATE(); | ||
| 427 | - FORCE_RET(); | ||
| 428 | -} | ||
| 429 | -FLOAT_OP(cvts, d) | ||
| 430 | -{ | ||
| 431 | - CALL_FROM_TB0(do_float_cvts_d); | ||
| 432 | - DEBUG_FPU_STATE(); | ||
| 433 | - FORCE_RET(); | ||
| 434 | -} | ||
| 435 | -FLOAT_OP(cvts, w) | ||
| 436 | -{ | ||
| 437 | - CALL_FROM_TB0(do_float_cvts_w); | ||
| 438 | - DEBUG_FPU_STATE(); | ||
| 439 | - FORCE_RET(); | ||
| 440 | -} | ||
| 441 | -FLOAT_OP(cvts, l) | ||
| 442 | -{ | ||
| 443 | - CALL_FROM_TB0(do_float_cvts_l); | ||
| 444 | - DEBUG_FPU_STATE(); | ||
| 445 | - FORCE_RET(); | ||
| 446 | -} | ||
| 447 | -FLOAT_OP(cvts, pl) | ||
| 448 | -{ | ||
| 449 | - CALL_FROM_TB0(do_float_cvts_pl); | ||
| 450 | - DEBUG_FPU_STATE(); | ||
| 451 | - FORCE_RET(); | ||
| 452 | -} | ||
| 453 | -FLOAT_OP(cvts, pu) | ||
| 454 | -{ | ||
| 455 | - CALL_FROM_TB0(do_float_cvts_pu); | ||
| 456 | - DEBUG_FPU_STATE(); | ||
| 457 | - FORCE_RET(); | ||
| 458 | -} | ||
| 459 | -FLOAT_OP(cvtw, s) | ||
| 460 | -{ | ||
| 461 | - CALL_FROM_TB0(do_float_cvtw_s); | ||
| 462 | - DEBUG_FPU_STATE(); | ||
| 463 | - FORCE_RET(); | ||
| 464 | -} | ||
| 465 | -FLOAT_OP(cvtw, d) | ||
| 466 | -{ | ||
| 467 | - CALL_FROM_TB0(do_float_cvtw_d); | ||
| 468 | - DEBUG_FPU_STATE(); | ||
| 469 | - FORCE_RET(); | ||
| 470 | -} | ||
| 471 | 387 | ||
| 472 | FLOAT_OP(pll, ps) | 388 | FLOAT_OP(pll, ps) |
| 473 | { | 389 | { |
| @@ -494,35 +410,6 @@ FLOAT_OP(puu, ps) | @@ -494,35 +410,6 @@ FLOAT_OP(puu, ps) | ||
| 494 | FORCE_RET(); | 410 | FORCE_RET(); |
| 495 | } | 411 | } |
| 496 | 412 | ||
| 497 | -#define FLOAT_ROUNDOP(op, ttype, stype) \ | ||
| 498 | -FLOAT_OP(op ## ttype, stype) \ | ||
| 499 | -{ \ | ||
| 500 | - CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \ | ||
| 501 | - DEBUG_FPU_STATE(); \ | ||
| 502 | - FORCE_RET(); \ | ||
| 503 | -} | ||
| 504 | - | ||
| 505 | -FLOAT_ROUNDOP(round, l, d) | ||
| 506 | -FLOAT_ROUNDOP(round, l, s) | ||
| 507 | -FLOAT_ROUNDOP(round, w, d) | ||
| 508 | -FLOAT_ROUNDOP(round, w, s) | ||
| 509 | - | ||
| 510 | -FLOAT_ROUNDOP(trunc, l, d) | ||
| 511 | -FLOAT_ROUNDOP(trunc, l, s) | ||
| 512 | -FLOAT_ROUNDOP(trunc, w, d) | ||
| 513 | -FLOAT_ROUNDOP(trunc, w, s) | ||
| 514 | - | ||
| 515 | -FLOAT_ROUNDOP(ceil, l, d) | ||
| 516 | -FLOAT_ROUNDOP(ceil, l, s) | ||
| 517 | -FLOAT_ROUNDOP(ceil, w, d) | ||
| 518 | -FLOAT_ROUNDOP(ceil, w, s) | ||
| 519 | - | ||
| 520 | -FLOAT_ROUNDOP(floor, l, d) | ||
| 521 | -FLOAT_ROUNDOP(floor, l, s) | ||
| 522 | -FLOAT_ROUNDOP(floor, w, d) | ||
| 523 | -FLOAT_ROUNDOP(floor, w, s) | ||
| 524 | -#undef FLOAR_ROUNDOP | ||
| 525 | - | ||
| 526 | FLOAT_OP(movf, d) | 413 | FLOAT_OP(movf, d) |
| 527 | { | 414 | { |
| 528 | if (!(env->fpu->fcr31 & PARAM1)) | 415 | if (!(env->fpu->fcr31 & PARAM1)) |
| @@ -618,66 +505,6 @@ FLOAT_OP(movn, ps) | @@ -618,66 +505,6 @@ FLOAT_OP(movn, ps) | ||
| 618 | FORCE_RET(); | 505 | FORCE_RET(); |
| 619 | } | 506 | } |
| 620 | 507 | ||
| 621 | -/* operations calling helpers, for s, d and ps */ | ||
| 622 | -#define FLOAT_HOP(name) \ | ||
| 623 | -FLOAT_OP(name, d) \ | ||
| 624 | -{ \ | ||
| 625 | - CALL_FROM_TB0(do_float_ ## name ## _d); \ | ||
| 626 | - DEBUG_FPU_STATE(); \ | ||
| 627 | - FORCE_RET(); \ | ||
| 628 | -} \ | ||
| 629 | -FLOAT_OP(name, s) \ | ||
| 630 | -{ \ | ||
| 631 | - CALL_FROM_TB0(do_float_ ## name ## _s); \ | ||
| 632 | - DEBUG_FPU_STATE(); \ | ||
| 633 | - FORCE_RET(); \ | ||
| 634 | -} \ | ||
| 635 | -FLOAT_OP(name, ps) \ | ||
| 636 | -{ \ | ||
| 637 | - CALL_FROM_TB0(do_float_ ## name ## _ps); \ | ||
| 638 | - DEBUG_FPU_STATE(); \ | ||
| 639 | - FORCE_RET(); \ | ||
| 640 | -} | ||
| 641 | -FLOAT_HOP(add) | ||
| 642 | -FLOAT_HOP(sub) | ||
| 643 | -FLOAT_HOP(mul) | ||
| 644 | -FLOAT_HOP(div) | ||
| 645 | -FLOAT_HOP(recip2) | ||
| 646 | -FLOAT_HOP(rsqrt2) | ||
| 647 | -FLOAT_HOP(rsqrt1) | ||
| 648 | -FLOAT_HOP(recip1) | ||
| 649 | -#undef FLOAT_HOP | ||
| 650 | - | ||
| 651 | -/* operations calling helpers, for s and d */ | ||
| 652 | -#define FLOAT_HOP(name) \ | ||
| 653 | -FLOAT_OP(name, d) \ | ||
| 654 | -{ \ | ||
| 655 | - CALL_FROM_TB0(do_float_ ## name ## _d); \ | ||
| 656 | - DEBUG_FPU_STATE(); \ | ||
| 657 | - FORCE_RET(); \ | ||
| 658 | -} \ | ||
| 659 | -FLOAT_OP(name, s) \ | ||
| 660 | -{ \ | ||
| 661 | - CALL_FROM_TB0(do_float_ ## name ## _s); \ | ||
| 662 | - DEBUG_FPU_STATE(); \ | ||
| 663 | - FORCE_RET(); \ | ||
| 664 | -} | ||
| 665 | -FLOAT_HOP(rsqrt) | ||
| 666 | -FLOAT_HOP(recip) | ||
| 667 | -#undef FLOAT_HOP | ||
| 668 | - | ||
| 669 | -/* operations calling helpers, for ps */ | ||
| 670 | -#define FLOAT_HOP(name) \ | ||
| 671 | -FLOAT_OP(name, ps) \ | ||
| 672 | -{ \ | ||
| 673 | - CALL_FROM_TB0(do_float_ ## name ## _ps); \ | ||
| 674 | - DEBUG_FPU_STATE(); \ | ||
| 675 | - FORCE_RET(); \ | ||
| 676 | -} | ||
| 677 | -FLOAT_HOP(addr) | ||
| 678 | -FLOAT_HOP(mulr) | ||
| 679 | -#undef FLOAT_HOP | ||
| 680 | - | ||
| 681 | /* ternary operations */ | 508 | /* ternary operations */ |
| 682 | #define FLOAT_TERNOP(name1, name2) \ | 509 | #define FLOAT_TERNOP(name1, name2) \ |
| 683 | FLOAT_OP(name1 ## name2, d) \ | 510 | FLOAT_OP(name1 ## name2, d) \ |
| @@ -836,43 +663,6 @@ FLOAT_OP(alnv, ps) | @@ -836,43 +663,6 @@ FLOAT_OP(alnv, ps) | ||
| 836 | 663 | ||
| 837 | extern void dump_fpu_s(CPUState *env); | 664 | extern void dump_fpu_s(CPUState *env); |
| 838 | 665 | ||
| 839 | -#define CMP_OP(fmt, op) \ | ||
| 840 | -void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \ | ||
| 841 | -{ \ | ||
| 842 | - CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \ | ||
| 843 | - DEBUG_FPU_STATE(); \ | ||
| 844 | - FORCE_RET(); \ | ||
| 845 | -} \ | ||
| 846 | -void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \ | ||
| 847 | -{ \ | ||
| 848 | - CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \ | ||
| 849 | - DEBUG_FPU_STATE(); \ | ||
| 850 | - FORCE_RET(); \ | ||
| 851 | -} | ||
| 852 | -#define CMP_OPS(op) \ | ||
| 853 | -CMP_OP(d, op) \ | ||
| 854 | -CMP_OP(s, op) \ | ||
| 855 | -CMP_OP(ps, op) | ||
| 856 | - | ||
| 857 | -CMP_OPS(f) | ||
| 858 | -CMP_OPS(un) | ||
| 859 | -CMP_OPS(eq) | ||
| 860 | -CMP_OPS(ueq) | ||
| 861 | -CMP_OPS(olt) | ||
| 862 | -CMP_OPS(ult) | ||
| 863 | -CMP_OPS(ole) | ||
| 864 | -CMP_OPS(ule) | ||
| 865 | -CMP_OPS(sf) | ||
| 866 | -CMP_OPS(ngle) | ||
| 867 | -CMP_OPS(seq) | ||
| 868 | -CMP_OPS(ngl) | ||
| 869 | -CMP_OPS(lt) | ||
| 870 | -CMP_OPS(nge) | ||
| 871 | -CMP_OPS(le) | ||
| 872 | -CMP_OPS(ngt) | ||
| 873 | -#undef CMP_OPS | ||
| 874 | -#undef CMP_OP | ||
| 875 | - | ||
| 876 | void op_bc1f (void) | 666 | void op_bc1f (void) |
| 877 | { | 667 | { |
| 878 | T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1)); | 668 | T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1)); |
target-mips/translate.c
| @@ -630,28 +630,28 @@ static inline void gen_store_fpr32h (TCGv t, int reg) | @@ -630,28 +630,28 @@ static inline void gen_store_fpr32h (TCGv t, int reg) | ||
| 630 | tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX); | 630 | tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX); |
| 631 | } | 631 | } |
| 632 | 632 | ||
| 633 | -#define FOP_CONDS(type, fmt) \ | ||
| 634 | -static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \ | ||
| 635 | - gen_op_cmp ## type ## _ ## fmt ## _f, \ | ||
| 636 | - gen_op_cmp ## type ## _ ## fmt ## _un, \ | ||
| 637 | - gen_op_cmp ## type ## _ ## fmt ## _eq, \ | ||
| 638 | - gen_op_cmp ## type ## _ ## fmt ## _ueq, \ | ||
| 639 | - gen_op_cmp ## type ## _ ## fmt ## _olt, \ | ||
| 640 | - gen_op_cmp ## type ## _ ## fmt ## _ult, \ | ||
| 641 | - gen_op_cmp ## type ## _ ## fmt ## _ole, \ | ||
| 642 | - gen_op_cmp ## type ## _ ## fmt ## _ule, \ | ||
| 643 | - gen_op_cmp ## type ## _ ## fmt ## _sf, \ | ||
| 644 | - gen_op_cmp ## type ## _ ## fmt ## _ngle, \ | ||
| 645 | - gen_op_cmp ## type ## _ ## fmt ## _seq, \ | ||
| 646 | - gen_op_cmp ## type ## _ ## fmt ## _ngl, \ | ||
| 647 | - gen_op_cmp ## type ## _ ## fmt ## _lt, \ | ||
| 648 | - gen_op_cmp ## type ## _ ## fmt ## _nge, \ | ||
| 649 | - gen_op_cmp ## type ## _ ## fmt ## _le, \ | ||
| 650 | - gen_op_cmp ## type ## _ ## fmt ## _ngt, \ | ||
| 651 | -}; \ | ||
| 652 | -static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \ | ||
| 653 | -{ \ | ||
| 654 | - gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \ | 633 | +#define FOP_CONDS(type, fmt) \ |
| 634 | +static GenOpFunc1 * fcmp ## type ## _ ## fmt ## _table[16] = { \ | ||
| 635 | + do_cmp ## type ## _ ## fmt ## _f, \ | ||
| 636 | + do_cmp ## type ## _ ## fmt ## _un, \ | ||
| 637 | + do_cmp ## type ## _ ## fmt ## _eq, \ | ||
| 638 | + do_cmp ## type ## _ ## fmt ## _ueq, \ | ||
| 639 | + do_cmp ## type ## _ ## fmt ## _olt, \ | ||
| 640 | + do_cmp ## type ## _ ## fmt ## _ult, \ | ||
| 641 | + do_cmp ## type ## _ ## fmt ## _ole, \ | ||
| 642 | + do_cmp ## type ## _ ## fmt ## _ule, \ | ||
| 643 | + do_cmp ## type ## _ ## fmt ## _sf, \ | ||
| 644 | + do_cmp ## type ## _ ## fmt ## _ngle, \ | ||
| 645 | + do_cmp ## type ## _ ## fmt ## _seq, \ | ||
| 646 | + do_cmp ## type ## _ ## fmt ## _ngl, \ | ||
| 647 | + do_cmp ## type ## _ ## fmt ## _lt, \ | ||
| 648 | + do_cmp ## type ## _ ## fmt ## _nge, \ | ||
| 649 | + do_cmp ## type ## _ ## fmt ## _le, \ | ||
| 650 | + do_cmp ## type ## _ ## fmt ## _ngt, \ | ||
| 651 | +}; \ | ||
| 652 | +static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \ | ||
| 653 | +{ \ | ||
| 654 | + tcg_gen_helper_0_1i(fcmp ## type ## _ ## fmt ## _table[n], cc); \ | ||
| 655 | } | 655 | } |
| 656 | 656 | ||
| 657 | FOP_CONDS(, d) | 657 | FOP_CONDS(, d) |
| @@ -660,6 +660,7 @@ FOP_CONDS(, s) | @@ -660,6 +660,7 @@ FOP_CONDS(, s) | ||
| 660 | FOP_CONDS(abs, s) | 660 | FOP_CONDS(abs, s) |
| 661 | FOP_CONDS(, ps) | 661 | FOP_CONDS(, ps) |
| 662 | FOP_CONDS(abs, ps) | 662 | FOP_CONDS(abs, ps) |
| 663 | +#undef FOP_CONDS | ||
| 663 | 664 | ||
| 664 | /* Tests */ | 665 | /* Tests */ |
| 665 | #define OP_COND(name, cond) \ | 666 | #define OP_COND(name, cond) \ |
| @@ -5597,7 +5598,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5597,7 +5598,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5597 | case FOP(0, 16): | 5598 | case FOP(0, 16): |
| 5598 | gen_load_fpr32(fpu32_T[0], fs); | 5599 | gen_load_fpr32(fpu32_T[0], fs); |
| 5599 | gen_load_fpr32(fpu32_T[1], ft); | 5600 | gen_load_fpr32(fpu32_T[1], ft); |
| 5600 | - gen_op_float_add_s(); | 5601 | + tcg_gen_helper_0_0(do_float_add_s); |
| 5601 | gen_store_fpr32(fpu32_T[2], fd); | 5602 | gen_store_fpr32(fpu32_T[2], fd); |
| 5602 | opn = "add.s"; | 5603 | opn = "add.s"; |
| 5603 | optype = BINOP; | 5604 | optype = BINOP; |
| @@ -5605,7 +5606,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5605,7 +5606,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5605 | case FOP(1, 16): | 5606 | case FOP(1, 16): |
| 5606 | gen_load_fpr32(fpu32_T[0], fs); | 5607 | gen_load_fpr32(fpu32_T[0], fs); |
| 5607 | gen_load_fpr32(fpu32_T[1], ft); | 5608 | gen_load_fpr32(fpu32_T[1], ft); |
| 5608 | - gen_op_float_sub_s(); | 5609 | + tcg_gen_helper_0_0(do_float_sub_s); |
| 5609 | gen_store_fpr32(fpu32_T[2], fd); | 5610 | gen_store_fpr32(fpu32_T[2], fd); |
| 5610 | opn = "sub.s"; | 5611 | opn = "sub.s"; |
| 5611 | optype = BINOP; | 5612 | optype = BINOP; |
| @@ -5613,7 +5614,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5613,7 +5614,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5613 | case FOP(2, 16): | 5614 | case FOP(2, 16): |
| 5614 | gen_load_fpr32(fpu32_T[0], fs); | 5615 | gen_load_fpr32(fpu32_T[0], fs); |
| 5615 | gen_load_fpr32(fpu32_T[1], ft); | 5616 | gen_load_fpr32(fpu32_T[1], ft); |
| 5616 | - gen_op_float_mul_s(); | 5617 | + tcg_gen_helper_0_0(do_float_mul_s); |
| 5617 | gen_store_fpr32(fpu32_T[2], fd); | 5618 | gen_store_fpr32(fpu32_T[2], fd); |
| 5618 | opn = "mul.s"; | 5619 | opn = "mul.s"; |
| 5619 | optype = BINOP; | 5620 | optype = BINOP; |
| @@ -5621,7 +5622,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5621,7 +5622,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5621 | case FOP(3, 16): | 5622 | case FOP(3, 16): |
| 5622 | gen_load_fpr32(fpu32_T[0], fs); | 5623 | gen_load_fpr32(fpu32_T[0], fs); |
| 5623 | gen_load_fpr32(fpu32_T[1], ft); | 5624 | gen_load_fpr32(fpu32_T[1], ft); |
| 5624 | - gen_op_float_div_s(); | 5625 | + tcg_gen_helper_0_0(do_float_div_s); |
| 5625 | gen_store_fpr32(fpu32_T[2], fd); | 5626 | gen_store_fpr32(fpu32_T[2], fd); |
| 5626 | opn = "div.s"; | 5627 | opn = "div.s"; |
| 5627 | optype = BINOP; | 5628 | optype = BINOP; |
| @@ -5653,52 +5654,52 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5653,52 +5654,52 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5653 | case FOP(8, 16): | 5654 | case FOP(8, 16): |
| 5654 | check_cp1_64bitmode(ctx); | 5655 | check_cp1_64bitmode(ctx); |
| 5655 | gen_load_fpr32(fpu32_T[0], fs); | 5656 | gen_load_fpr32(fpu32_T[0], fs); |
| 5656 | - gen_op_float_roundl_s(); | 5657 | + tcg_gen_helper_0_0(do_float_roundl_s); |
| 5657 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5658 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5658 | opn = "round.l.s"; | 5659 | opn = "round.l.s"; |
| 5659 | break; | 5660 | break; |
| 5660 | case FOP(9, 16): | 5661 | case FOP(9, 16): |
| 5661 | check_cp1_64bitmode(ctx); | 5662 | check_cp1_64bitmode(ctx); |
| 5662 | gen_load_fpr32(fpu32_T[0], fs); | 5663 | gen_load_fpr32(fpu32_T[0], fs); |
| 5663 | - gen_op_float_truncl_s(); | 5664 | + tcg_gen_helper_0_0(do_float_truncl_s); |
| 5664 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5665 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5665 | opn = "trunc.l.s"; | 5666 | opn = "trunc.l.s"; |
| 5666 | break; | 5667 | break; |
| 5667 | case FOP(10, 16): | 5668 | case FOP(10, 16): |
| 5668 | check_cp1_64bitmode(ctx); | 5669 | check_cp1_64bitmode(ctx); |
| 5669 | gen_load_fpr32(fpu32_T[0], fs); | 5670 | gen_load_fpr32(fpu32_T[0], fs); |
| 5670 | - gen_op_float_ceill_s(); | 5671 | + tcg_gen_helper_0_0(do_float_ceill_s); |
| 5671 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5672 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5672 | opn = "ceil.l.s"; | 5673 | opn = "ceil.l.s"; |
| 5673 | break; | 5674 | break; |
| 5674 | case FOP(11, 16): | 5675 | case FOP(11, 16): |
| 5675 | check_cp1_64bitmode(ctx); | 5676 | check_cp1_64bitmode(ctx); |
| 5676 | gen_load_fpr32(fpu32_T[0], fs); | 5677 | gen_load_fpr32(fpu32_T[0], fs); |
| 5677 | - gen_op_float_floorl_s(); | 5678 | + tcg_gen_helper_0_0(do_float_floorl_s); |
| 5678 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5679 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5679 | opn = "floor.l.s"; | 5680 | opn = "floor.l.s"; |
| 5680 | break; | 5681 | break; |
| 5681 | case FOP(12, 16): | 5682 | case FOP(12, 16): |
| 5682 | gen_load_fpr32(fpu32_T[0], fs); | 5683 | gen_load_fpr32(fpu32_T[0], fs); |
| 5683 | - gen_op_float_roundw_s(); | 5684 | + tcg_gen_helper_0_0(do_float_roundw_s); |
| 5684 | gen_store_fpr32(fpu32_T[2], fd); | 5685 | gen_store_fpr32(fpu32_T[2], fd); |
| 5685 | opn = "round.w.s"; | 5686 | opn = "round.w.s"; |
| 5686 | break; | 5687 | break; |
| 5687 | case FOP(13, 16): | 5688 | case FOP(13, 16): |
| 5688 | gen_load_fpr32(fpu32_T[0], fs); | 5689 | gen_load_fpr32(fpu32_T[0], fs); |
| 5689 | - gen_op_float_truncw_s(); | 5690 | + tcg_gen_helper_0_0(do_float_truncw_s); |
| 5690 | gen_store_fpr32(fpu32_T[2], fd); | 5691 | gen_store_fpr32(fpu32_T[2], fd); |
| 5691 | opn = "trunc.w.s"; | 5692 | opn = "trunc.w.s"; |
| 5692 | break; | 5693 | break; |
| 5693 | case FOP(14, 16): | 5694 | case FOP(14, 16): |
| 5694 | gen_load_fpr32(fpu32_T[0], fs); | 5695 | gen_load_fpr32(fpu32_T[0], fs); |
| 5695 | - gen_op_float_ceilw_s(); | 5696 | + tcg_gen_helper_0_0(do_float_ceilw_s); |
| 5696 | gen_store_fpr32(fpu32_T[2], fd); | 5697 | gen_store_fpr32(fpu32_T[2], fd); |
| 5697 | opn = "ceil.w.s"; | 5698 | opn = "ceil.w.s"; |
| 5698 | break; | 5699 | break; |
| 5699 | case FOP(15, 16): | 5700 | case FOP(15, 16): |
| 5700 | gen_load_fpr32(fpu32_T[0], fs); | 5701 | gen_load_fpr32(fpu32_T[0], fs); |
| 5701 | - gen_op_float_floorw_s(); | 5702 | + tcg_gen_helper_0_0(do_float_floorw_s); |
| 5702 | gen_store_fpr32(fpu32_T[2], fd); | 5703 | gen_store_fpr32(fpu32_T[2], fd); |
| 5703 | opn = "floor.w.s"; | 5704 | opn = "floor.w.s"; |
| 5704 | break; | 5705 | break; |
| @@ -5729,14 +5730,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5729,14 +5730,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5729 | case FOP(21, 16): | 5730 | case FOP(21, 16): |
| 5730 | check_cop1x(ctx); | 5731 | check_cop1x(ctx); |
| 5731 | gen_load_fpr32(fpu32_T[0], fs); | 5732 | gen_load_fpr32(fpu32_T[0], fs); |
| 5732 | - gen_op_float_recip_s(); | 5733 | + tcg_gen_helper_0_0(do_float_recip_s); |
| 5733 | gen_store_fpr32(fpu32_T[2], fd); | 5734 | gen_store_fpr32(fpu32_T[2], fd); |
| 5734 | opn = "recip.s"; | 5735 | opn = "recip.s"; |
| 5735 | break; | 5736 | break; |
| 5736 | case FOP(22, 16): | 5737 | case FOP(22, 16): |
| 5737 | check_cop1x(ctx); | 5738 | check_cop1x(ctx); |
| 5738 | gen_load_fpr32(fpu32_T[0], fs); | 5739 | gen_load_fpr32(fpu32_T[0], fs); |
| 5739 | - gen_op_float_rsqrt_s(); | 5740 | + tcg_gen_helper_0_0(do_float_rsqrt_s); |
| 5740 | gen_store_fpr32(fpu32_T[2], fd); | 5741 | gen_store_fpr32(fpu32_T[2], fd); |
| 5741 | opn = "rsqrt.s"; | 5742 | opn = "rsqrt.s"; |
| 5742 | break; | 5743 | break; |
| @@ -5744,21 +5745,21 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5744,21 +5745,21 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5744 | check_cp1_64bitmode(ctx); | 5745 | check_cp1_64bitmode(ctx); |
| 5745 | gen_load_fpr32(fpu32_T[0], fs); | 5746 | gen_load_fpr32(fpu32_T[0], fs); |
| 5746 | gen_load_fpr32(fpu32_T[2], fd); | 5747 | gen_load_fpr32(fpu32_T[2], fd); |
| 5747 | - gen_op_float_recip2_s(); | 5748 | + tcg_gen_helper_0_0(do_float_recip2_s); |
| 5748 | gen_store_fpr32(fpu32_T[2], fd); | 5749 | gen_store_fpr32(fpu32_T[2], fd); |
| 5749 | opn = "recip2.s"; | 5750 | opn = "recip2.s"; |
| 5750 | break; | 5751 | break; |
| 5751 | case FOP(29, 16): | 5752 | case FOP(29, 16): |
| 5752 | check_cp1_64bitmode(ctx); | 5753 | check_cp1_64bitmode(ctx); |
| 5753 | gen_load_fpr32(fpu32_T[0], fs); | 5754 | gen_load_fpr32(fpu32_T[0], fs); |
| 5754 | - gen_op_float_recip1_s(); | 5755 | + tcg_gen_helper_0_0(do_float_recip1_s); |
| 5755 | gen_store_fpr32(fpu32_T[2], fd); | 5756 | gen_store_fpr32(fpu32_T[2], fd); |
| 5756 | opn = "recip1.s"; | 5757 | opn = "recip1.s"; |
| 5757 | break; | 5758 | break; |
| 5758 | case FOP(30, 16): | 5759 | case FOP(30, 16): |
| 5759 | check_cp1_64bitmode(ctx); | 5760 | check_cp1_64bitmode(ctx); |
| 5760 | gen_load_fpr32(fpu32_T[0], fs); | 5761 | gen_load_fpr32(fpu32_T[0], fs); |
| 5761 | - gen_op_float_rsqrt1_s(); | 5762 | + tcg_gen_helper_0_0(do_float_rsqrt1_s); |
| 5762 | gen_store_fpr32(fpu32_T[2], fd); | 5763 | gen_store_fpr32(fpu32_T[2], fd); |
| 5763 | opn = "rsqrt1.s"; | 5764 | opn = "rsqrt1.s"; |
| 5764 | break; | 5765 | break; |
| @@ -5766,27 +5767,27 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5766,27 +5767,27 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5766 | check_cp1_64bitmode(ctx); | 5767 | check_cp1_64bitmode(ctx); |
| 5767 | gen_load_fpr32(fpu32_T[0], fs); | 5768 | gen_load_fpr32(fpu32_T[0], fs); |
| 5768 | gen_load_fpr32(fpu32_T[2], ft); | 5769 | gen_load_fpr32(fpu32_T[2], ft); |
| 5769 | - gen_op_float_rsqrt2_s(); | 5770 | + tcg_gen_helper_0_0(do_float_rsqrt2_s); |
| 5770 | gen_store_fpr32(fpu32_T[2], fd); | 5771 | gen_store_fpr32(fpu32_T[2], fd); |
| 5771 | opn = "rsqrt2.s"; | 5772 | opn = "rsqrt2.s"; |
| 5772 | break; | 5773 | break; |
| 5773 | case FOP(33, 16): | 5774 | case FOP(33, 16): |
| 5774 | check_cp1_registers(ctx, fd); | 5775 | check_cp1_registers(ctx, fd); |
| 5775 | gen_load_fpr32(fpu32_T[0], fs); | 5776 | gen_load_fpr32(fpu32_T[0], fs); |
| 5776 | - gen_op_float_cvtd_s(); | 5777 | + tcg_gen_helper_0_0(do_float_cvtd_s); |
| 5777 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5778 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5778 | opn = "cvt.d.s"; | 5779 | opn = "cvt.d.s"; |
| 5779 | break; | 5780 | break; |
| 5780 | case FOP(36, 16): | 5781 | case FOP(36, 16): |
| 5781 | gen_load_fpr32(fpu32_T[0], fs); | 5782 | gen_load_fpr32(fpu32_T[0], fs); |
| 5782 | - gen_op_float_cvtw_s(); | 5783 | + tcg_gen_helper_0_0(do_float_cvtw_s); |
| 5783 | gen_store_fpr32(fpu32_T[2], fd); | 5784 | gen_store_fpr32(fpu32_T[2], fd); |
| 5784 | opn = "cvt.w.s"; | 5785 | opn = "cvt.w.s"; |
| 5785 | break; | 5786 | break; |
| 5786 | case FOP(37, 16): | 5787 | case FOP(37, 16): |
| 5787 | check_cp1_64bitmode(ctx); | 5788 | check_cp1_64bitmode(ctx); |
| 5788 | gen_load_fpr32(fpu32_T[0], fs); | 5789 | gen_load_fpr32(fpu32_T[0], fs); |
| 5789 | - gen_op_float_cvtl_s(); | 5790 | + tcg_gen_helper_0_0(do_float_cvtl_s); |
| 5790 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5791 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5791 | opn = "cvt.l.s"; | 5792 | opn = "cvt.l.s"; |
| 5792 | break; | 5793 | break; |
| @@ -5829,7 +5830,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5829,7 +5830,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5829 | check_cp1_registers(ctx, fs | ft | fd); | 5830 | check_cp1_registers(ctx, fs | ft | fd); |
| 5830 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5831 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5831 | gen_load_fpr64(ctx, fpu64_T[1], ft); | 5832 | gen_load_fpr64(ctx, fpu64_T[1], ft); |
| 5832 | - gen_op_float_add_d(); | 5833 | + tcg_gen_helper_0_0(do_float_add_d); |
| 5833 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5834 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5834 | opn = "add.d"; | 5835 | opn = "add.d"; |
| 5835 | optype = BINOP; | 5836 | optype = BINOP; |
| @@ -5838,7 +5839,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5838,7 +5839,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5838 | check_cp1_registers(ctx, fs | ft | fd); | 5839 | check_cp1_registers(ctx, fs | ft | fd); |
| 5839 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5840 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5840 | gen_load_fpr64(ctx, fpu64_T[1], ft); | 5841 | gen_load_fpr64(ctx, fpu64_T[1], ft); |
| 5841 | - gen_op_float_sub_d(); | 5842 | + tcg_gen_helper_0_0(do_float_sub_d); |
| 5842 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5843 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5843 | opn = "sub.d"; | 5844 | opn = "sub.d"; |
| 5844 | optype = BINOP; | 5845 | optype = BINOP; |
| @@ -5847,7 +5848,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5847,7 +5848,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5847 | check_cp1_registers(ctx, fs | ft | fd); | 5848 | check_cp1_registers(ctx, fs | ft | fd); |
| 5848 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5849 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5849 | gen_load_fpr64(ctx, fpu64_T[1], ft); | 5850 | gen_load_fpr64(ctx, fpu64_T[1], ft); |
| 5850 | - gen_op_float_mul_d(); | 5851 | + tcg_gen_helper_0_0(do_float_mul_d); |
| 5851 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5852 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5852 | opn = "mul.d"; | 5853 | opn = "mul.d"; |
| 5853 | optype = BINOP; | 5854 | optype = BINOP; |
| @@ -5856,7 +5857,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5856,7 +5857,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5856 | check_cp1_registers(ctx, fs | ft | fd); | 5857 | check_cp1_registers(ctx, fs | ft | fd); |
| 5857 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5858 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5858 | gen_load_fpr64(ctx, fpu64_T[1], ft); | 5859 | gen_load_fpr64(ctx, fpu64_T[1], ft); |
| 5859 | - gen_op_float_div_d(); | 5860 | + tcg_gen_helper_0_0(do_float_div_d); |
| 5860 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5861 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5861 | opn = "div.d"; | 5862 | opn = "div.d"; |
| 5862 | optype = BINOP; | 5863 | optype = BINOP; |
| @@ -5892,56 +5893,56 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5892,56 +5893,56 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5892 | case FOP(8, 17): | 5893 | case FOP(8, 17): |
| 5893 | check_cp1_64bitmode(ctx); | 5894 | check_cp1_64bitmode(ctx); |
| 5894 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5895 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5895 | - gen_op_float_roundl_d(); | 5896 | + tcg_gen_helper_0_0(do_float_roundl_d); |
| 5896 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5897 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5897 | opn = "round.l.d"; | 5898 | opn = "round.l.d"; |
| 5898 | break; | 5899 | break; |
| 5899 | case FOP(9, 17): | 5900 | case FOP(9, 17): |
| 5900 | check_cp1_64bitmode(ctx); | 5901 | check_cp1_64bitmode(ctx); |
| 5901 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5902 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5902 | - gen_op_float_truncl_d(); | 5903 | + tcg_gen_helper_0_0(do_float_truncl_d); |
| 5903 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5904 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5904 | opn = "trunc.l.d"; | 5905 | opn = "trunc.l.d"; |
| 5905 | break; | 5906 | break; |
| 5906 | case FOP(10, 17): | 5907 | case FOP(10, 17): |
| 5907 | check_cp1_64bitmode(ctx); | 5908 | check_cp1_64bitmode(ctx); |
| 5908 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5909 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5909 | - gen_op_float_ceill_d(); | 5910 | + tcg_gen_helper_0_0(do_float_ceill_d); |
| 5910 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5911 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5911 | opn = "ceil.l.d"; | 5912 | opn = "ceil.l.d"; |
| 5912 | break; | 5913 | break; |
| 5913 | case FOP(11, 17): | 5914 | case FOP(11, 17): |
| 5914 | check_cp1_64bitmode(ctx); | 5915 | check_cp1_64bitmode(ctx); |
| 5915 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5916 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5916 | - gen_op_float_floorl_d(); | 5917 | + tcg_gen_helper_0_0(do_float_floorl_d); |
| 5917 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5918 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5918 | opn = "floor.l.d"; | 5919 | opn = "floor.l.d"; |
| 5919 | break; | 5920 | break; |
| 5920 | case FOP(12, 17): | 5921 | case FOP(12, 17): |
| 5921 | check_cp1_registers(ctx, fs); | 5922 | check_cp1_registers(ctx, fs); |
| 5922 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5923 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5923 | - gen_op_float_roundw_d(); | 5924 | + tcg_gen_helper_0_0(do_float_roundw_d); |
| 5924 | gen_store_fpr32(fpu32_T[2], fd); | 5925 | gen_store_fpr32(fpu32_T[2], fd); |
| 5925 | opn = "round.w.d"; | 5926 | opn = "round.w.d"; |
| 5926 | break; | 5927 | break; |
| 5927 | case FOP(13, 17): | 5928 | case FOP(13, 17): |
| 5928 | check_cp1_registers(ctx, fs); | 5929 | check_cp1_registers(ctx, fs); |
| 5929 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5930 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5930 | - gen_op_float_truncw_d(); | 5931 | + tcg_gen_helper_0_0(do_float_truncw_d); |
| 5931 | gen_store_fpr32(fpu32_T[2], fd); | 5932 | gen_store_fpr32(fpu32_T[2], fd); |
| 5932 | opn = "trunc.w.d"; | 5933 | opn = "trunc.w.d"; |
| 5933 | break; | 5934 | break; |
| 5934 | case FOP(14, 17): | 5935 | case FOP(14, 17): |
| 5935 | check_cp1_registers(ctx, fs); | 5936 | check_cp1_registers(ctx, fs); |
| 5936 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5937 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5937 | - gen_op_float_ceilw_d(); | 5938 | + tcg_gen_helper_0_0(do_float_ceilw_d); |
| 5938 | gen_store_fpr32(fpu32_T[2], fd); | 5939 | gen_store_fpr32(fpu32_T[2], fd); |
| 5939 | opn = "ceil.w.d"; | 5940 | opn = "ceil.w.d"; |
| 5940 | break; | 5941 | break; |
| 5941 | case FOP(15, 17): | 5942 | case FOP(15, 17): |
| 5942 | check_cp1_registers(ctx, fs); | 5943 | check_cp1_registers(ctx, fs); |
| 5943 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5944 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5944 | - gen_op_float_floorw_d(); | 5945 | + tcg_gen_helper_0_0(do_float_floorw_d); |
| 5945 | gen_store_fpr32(fpu32_T[2], fd); | 5946 | gen_store_fpr32(fpu32_T[2], fd); |
| 5946 | opn = "floor.w.d"; | 5947 | opn = "floor.w.d"; |
| 5947 | break; | 5948 | break; |
| @@ -5972,14 +5973,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5972,14 +5973,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5972 | case FOP(21, 17): | 5973 | case FOP(21, 17): |
| 5973 | check_cp1_64bitmode(ctx); | 5974 | check_cp1_64bitmode(ctx); |
| 5974 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5975 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5975 | - gen_op_float_recip_d(); | 5976 | + tcg_gen_helper_0_0(do_float_recip_d); |
| 5976 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5977 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5977 | opn = "recip.d"; | 5978 | opn = "recip.d"; |
| 5978 | break; | 5979 | break; |
| 5979 | case FOP(22, 17): | 5980 | case FOP(22, 17): |
| 5980 | check_cp1_64bitmode(ctx); | 5981 | check_cp1_64bitmode(ctx); |
| 5981 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5982 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5982 | - gen_op_float_rsqrt_d(); | 5983 | + tcg_gen_helper_0_0(do_float_rsqrt_d); |
| 5983 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5984 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5984 | opn = "rsqrt.d"; | 5985 | opn = "rsqrt.d"; |
| 5985 | break; | 5986 | break; |
| @@ -5987,21 +5988,21 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -5987,21 +5988,21 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 5987 | check_cp1_64bitmode(ctx); | 5988 | check_cp1_64bitmode(ctx); |
| 5988 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5989 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5989 | gen_load_fpr64(ctx, fpu64_T[2], ft); | 5990 | gen_load_fpr64(ctx, fpu64_T[2], ft); |
| 5990 | - gen_op_float_recip2_d(); | 5991 | + tcg_gen_helper_0_0(do_float_recip2_d); |
| 5991 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5992 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5992 | opn = "recip2.d"; | 5993 | opn = "recip2.d"; |
| 5993 | break; | 5994 | break; |
| 5994 | case FOP(29, 17): | 5995 | case FOP(29, 17): |
| 5995 | check_cp1_64bitmode(ctx); | 5996 | check_cp1_64bitmode(ctx); |
| 5996 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 5997 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 5997 | - gen_op_float_recip1_d(); | 5998 | + tcg_gen_helper_0_0(do_float_recip1_d); |
| 5998 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 5999 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 5999 | opn = "recip1.d"; | 6000 | opn = "recip1.d"; |
| 6000 | break; | 6001 | break; |
| 6001 | case FOP(30, 17): | 6002 | case FOP(30, 17): |
| 6002 | check_cp1_64bitmode(ctx); | 6003 | check_cp1_64bitmode(ctx); |
| 6003 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 6004 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 6004 | - gen_op_float_rsqrt1_d(); | 6005 | + tcg_gen_helper_0_0(do_float_rsqrt1_d); |
| 6005 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 6006 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 6006 | opn = "rsqrt1.d"; | 6007 | opn = "rsqrt1.d"; |
| 6007 | break; | 6008 | break; |
| @@ -6009,7 +6010,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6009,7 +6010,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6009 | check_cp1_64bitmode(ctx); | 6010 | check_cp1_64bitmode(ctx); |
| 6010 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 6011 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 6011 | gen_load_fpr64(ctx, fpu64_T[2], ft); | 6012 | gen_load_fpr64(ctx, fpu64_T[2], ft); |
| 6012 | - gen_op_float_rsqrt2_d(); | 6013 | + tcg_gen_helper_0_0(do_float_rsqrt2_d); |
| 6013 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 6014 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 6014 | opn = "rsqrt2.d"; | 6015 | opn = "rsqrt2.d"; |
| 6015 | break; | 6016 | break; |
| @@ -6045,48 +6046,48 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6045,48 +6046,48 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6045 | case FOP(32, 17): | 6046 | case FOP(32, 17): |
| 6046 | check_cp1_registers(ctx, fs); | 6047 | check_cp1_registers(ctx, fs); |
| 6047 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 6048 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 6048 | - gen_op_float_cvts_d(); | 6049 | + tcg_gen_helper_0_0(do_float_cvts_d); |
| 6049 | gen_store_fpr32(fpu32_T[2], fd); | 6050 | gen_store_fpr32(fpu32_T[2], fd); |
| 6050 | opn = "cvt.s.d"; | 6051 | opn = "cvt.s.d"; |
| 6051 | break; | 6052 | break; |
| 6052 | case FOP(36, 17): | 6053 | case FOP(36, 17): |
| 6053 | check_cp1_registers(ctx, fs); | 6054 | check_cp1_registers(ctx, fs); |
| 6054 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 6055 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 6055 | - gen_op_float_cvtw_d(); | 6056 | + tcg_gen_helper_0_0(do_float_cvtw_d); |
| 6056 | gen_store_fpr32(fpu32_T[2], fd); | 6057 | gen_store_fpr32(fpu32_T[2], fd); |
| 6057 | opn = "cvt.w.d"; | 6058 | opn = "cvt.w.d"; |
| 6058 | break; | 6059 | break; |
| 6059 | case FOP(37, 17): | 6060 | case FOP(37, 17): |
| 6060 | check_cp1_64bitmode(ctx); | 6061 | check_cp1_64bitmode(ctx); |
| 6061 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 6062 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 6062 | - gen_op_float_cvtl_d(); | 6063 | + tcg_gen_helper_0_0(do_float_cvtl_d); |
| 6063 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 6064 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 6064 | opn = "cvt.l.d"; | 6065 | opn = "cvt.l.d"; |
| 6065 | break; | 6066 | break; |
| 6066 | case FOP(32, 20): | 6067 | case FOP(32, 20): |
| 6067 | gen_load_fpr32(fpu32_T[0], fs); | 6068 | gen_load_fpr32(fpu32_T[0], fs); |
| 6068 | - gen_op_float_cvts_w(); | 6069 | + tcg_gen_helper_0_0(do_float_cvts_w); |
| 6069 | gen_store_fpr32(fpu32_T[2], fd); | 6070 | gen_store_fpr32(fpu32_T[2], fd); |
| 6070 | opn = "cvt.s.w"; | 6071 | opn = "cvt.s.w"; |
| 6071 | break; | 6072 | break; |
| 6072 | case FOP(33, 20): | 6073 | case FOP(33, 20): |
| 6073 | check_cp1_registers(ctx, fd); | 6074 | check_cp1_registers(ctx, fd); |
| 6074 | gen_load_fpr32(fpu32_T[0], fs); | 6075 | gen_load_fpr32(fpu32_T[0], fs); |
| 6075 | - gen_op_float_cvtd_w(); | 6076 | + tcg_gen_helper_0_0(do_float_cvtd_w); |
| 6076 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 6077 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 6077 | opn = "cvt.d.w"; | 6078 | opn = "cvt.d.w"; |
| 6078 | break; | 6079 | break; |
| 6079 | case FOP(32, 21): | 6080 | case FOP(32, 21): |
| 6080 | check_cp1_64bitmode(ctx); | 6081 | check_cp1_64bitmode(ctx); |
| 6081 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 6082 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 6082 | - gen_op_float_cvts_l(); | 6083 | + tcg_gen_helper_0_0(do_float_cvts_l); |
| 6083 | gen_store_fpr32(fpu32_T[2], fd); | 6084 | gen_store_fpr32(fpu32_T[2], fd); |
| 6084 | opn = "cvt.s.l"; | 6085 | opn = "cvt.s.l"; |
| 6085 | break; | 6086 | break; |
| 6086 | case FOP(33, 21): | 6087 | case FOP(33, 21): |
| 6087 | check_cp1_64bitmode(ctx); | 6088 | check_cp1_64bitmode(ctx); |
| 6088 | gen_load_fpr64(ctx, fpu64_T[0], fs); | 6089 | gen_load_fpr64(ctx, fpu64_T[0], fs); |
| 6089 | - gen_op_float_cvtd_l(); | 6090 | + tcg_gen_helper_0_0(do_float_cvtd_l); |
| 6090 | gen_store_fpr64(ctx, fpu64_T[2], fd); | 6091 | gen_store_fpr64(ctx, fpu64_T[2], fd); |
| 6091 | opn = "cvt.d.l"; | 6092 | opn = "cvt.d.l"; |
| 6092 | break; | 6093 | break; |
| @@ -6094,7 +6095,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6094,7 +6095,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6094 | check_cp1_64bitmode(ctx); | 6095 | check_cp1_64bitmode(ctx); |
| 6095 | gen_load_fpr32(fpu32_T[0], fs); | 6096 | gen_load_fpr32(fpu32_T[0], fs); |
| 6096 | gen_load_fpr32h(fpu32h_T[0], fs); | 6097 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6097 | - gen_op_float_cvtps_pw(); | 6098 | + tcg_gen_helper_0_0(do_float_cvtps_pw); |
| 6098 | gen_store_fpr32(fpu32_T[2], fd); | 6099 | gen_store_fpr32(fpu32_T[2], fd); |
| 6099 | gen_store_fpr32h(fpu32h_T[2], fd); | 6100 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6100 | opn = "cvt.ps.pw"; | 6101 | opn = "cvt.ps.pw"; |
| @@ -6105,7 +6106,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6105,7 +6106,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6105 | gen_load_fpr32h(fpu32h_T[0], fs); | 6106 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6106 | gen_load_fpr32(fpu32_T[1], ft); | 6107 | gen_load_fpr32(fpu32_T[1], ft); |
| 6107 | gen_load_fpr32h(fpu32h_T[1], ft); | 6108 | gen_load_fpr32h(fpu32h_T[1], ft); |
| 6108 | - gen_op_float_add_ps(); | 6109 | + tcg_gen_helper_0_0(do_float_add_ps); |
| 6109 | gen_store_fpr32(fpu32_T[2], fd); | 6110 | gen_store_fpr32(fpu32_T[2], fd); |
| 6110 | gen_store_fpr32h(fpu32h_T[2], fd); | 6111 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6111 | opn = "add.ps"; | 6112 | opn = "add.ps"; |
| @@ -6116,7 +6117,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6116,7 +6117,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6116 | gen_load_fpr32h(fpu32h_T[0], fs); | 6117 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6117 | gen_load_fpr32(fpu32_T[1], ft); | 6118 | gen_load_fpr32(fpu32_T[1], ft); |
| 6118 | gen_load_fpr32h(fpu32h_T[1], ft); | 6119 | gen_load_fpr32h(fpu32h_T[1], ft); |
| 6119 | - gen_op_float_sub_ps(); | 6120 | + tcg_gen_helper_0_0(do_float_sub_ps); |
| 6120 | gen_store_fpr32(fpu32_T[2], fd); | 6121 | gen_store_fpr32(fpu32_T[2], fd); |
| 6121 | gen_store_fpr32h(fpu32h_T[2], fd); | 6122 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6122 | opn = "sub.ps"; | 6123 | opn = "sub.ps"; |
| @@ -6127,7 +6128,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6127,7 +6128,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6127 | gen_load_fpr32h(fpu32h_T[0], fs); | 6128 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6128 | gen_load_fpr32(fpu32_T[1], ft); | 6129 | gen_load_fpr32(fpu32_T[1], ft); |
| 6129 | gen_load_fpr32h(fpu32h_T[1], ft); | 6130 | gen_load_fpr32h(fpu32h_T[1], ft); |
| 6130 | - gen_op_float_mul_ps(); | 6131 | + tcg_gen_helper_0_0(do_float_mul_ps); |
| 6131 | gen_store_fpr32(fpu32_T[2], fd); | 6132 | gen_store_fpr32(fpu32_T[2], fd); |
| 6132 | gen_store_fpr32h(fpu32h_T[2], fd); | 6133 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6133 | opn = "mul.ps"; | 6134 | opn = "mul.ps"; |
| @@ -6204,7 +6205,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6204,7 +6205,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6204 | gen_load_fpr32h(fpu32h_T[0], ft); | 6205 | gen_load_fpr32h(fpu32h_T[0], ft); |
| 6205 | gen_load_fpr32(fpu32_T[1], fs); | 6206 | gen_load_fpr32(fpu32_T[1], fs); |
| 6206 | gen_load_fpr32h(fpu32h_T[1], fs); | 6207 | gen_load_fpr32h(fpu32h_T[1], fs); |
| 6207 | - gen_op_float_addr_ps(); | 6208 | + tcg_gen_helper_0_0(do_float_addr_ps); |
| 6208 | gen_store_fpr32(fpu32_T[2], fd); | 6209 | gen_store_fpr32(fpu32_T[2], fd); |
| 6209 | gen_store_fpr32h(fpu32h_T[2], fd); | 6210 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6210 | opn = "addr.ps"; | 6211 | opn = "addr.ps"; |
| @@ -6215,7 +6216,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6215,7 +6216,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6215 | gen_load_fpr32h(fpu32h_T[0], ft); | 6216 | gen_load_fpr32h(fpu32h_T[0], ft); |
| 6216 | gen_load_fpr32(fpu32_T[1], fs); | 6217 | gen_load_fpr32(fpu32_T[1], fs); |
| 6217 | gen_load_fpr32h(fpu32h_T[1], fs); | 6218 | gen_load_fpr32h(fpu32h_T[1], fs); |
| 6218 | - gen_op_float_mulr_ps(); | 6219 | + tcg_gen_helper_0_0(do_float_mulr_ps); |
| 6219 | gen_store_fpr32(fpu32_T[2], fd); | 6220 | gen_store_fpr32(fpu32_T[2], fd); |
| 6220 | gen_store_fpr32h(fpu32h_T[2], fd); | 6221 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6221 | opn = "mulr.ps"; | 6222 | opn = "mulr.ps"; |
| @@ -6226,7 +6227,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6226,7 +6227,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6226 | gen_load_fpr32h(fpu32h_T[0], fs); | 6227 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6227 | gen_load_fpr32(fpu32_T[2], fd); | 6228 | gen_load_fpr32(fpu32_T[2], fd); |
| 6228 | gen_load_fpr32h(fpu32h_T[2], fd); | 6229 | gen_load_fpr32h(fpu32h_T[2], fd); |
| 6229 | - gen_op_float_recip2_ps(); | 6230 | + tcg_gen_helper_0_0(do_float_recip2_ps); |
| 6230 | gen_store_fpr32(fpu32_T[2], fd); | 6231 | gen_store_fpr32(fpu32_T[2], fd); |
| 6231 | gen_store_fpr32h(fpu32h_T[2], fd); | 6232 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6232 | opn = "recip2.ps"; | 6233 | opn = "recip2.ps"; |
| @@ -6235,7 +6236,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6235,7 +6236,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6235 | check_cp1_64bitmode(ctx); | 6236 | check_cp1_64bitmode(ctx); |
| 6236 | gen_load_fpr32(fpu32_T[0], fs); | 6237 | gen_load_fpr32(fpu32_T[0], fs); |
| 6237 | gen_load_fpr32h(fpu32h_T[0], fs); | 6238 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6238 | - gen_op_float_recip1_ps(); | 6239 | + tcg_gen_helper_0_0(do_float_recip1_ps); |
| 6239 | gen_store_fpr32(fpu32_T[2], fd); | 6240 | gen_store_fpr32(fpu32_T[2], fd); |
| 6240 | gen_store_fpr32h(fpu32h_T[2], fd); | 6241 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6241 | opn = "recip1.ps"; | 6242 | opn = "recip1.ps"; |
| @@ -6244,7 +6245,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6244,7 +6245,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6244 | check_cp1_64bitmode(ctx); | 6245 | check_cp1_64bitmode(ctx); |
| 6245 | gen_load_fpr32(fpu32_T[0], fs); | 6246 | gen_load_fpr32(fpu32_T[0], fs); |
| 6246 | gen_load_fpr32h(fpu32h_T[0], fs); | 6247 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6247 | - gen_op_float_rsqrt1_ps(); | 6248 | + tcg_gen_helper_0_0(do_float_rsqrt1_ps); |
| 6248 | gen_store_fpr32(fpu32_T[2], fd); | 6249 | gen_store_fpr32(fpu32_T[2], fd); |
| 6249 | gen_store_fpr32h(fpu32h_T[2], fd); | 6250 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6250 | opn = "rsqrt1.ps"; | 6251 | opn = "rsqrt1.ps"; |
| @@ -6255,7 +6256,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6255,7 +6256,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6255 | gen_load_fpr32h(fpu32h_T[0], fs); | 6256 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6256 | gen_load_fpr32(fpu32_T[2], ft); | 6257 | gen_load_fpr32(fpu32_T[2], ft); |
| 6257 | gen_load_fpr32h(fpu32h_T[2], ft); | 6258 | gen_load_fpr32h(fpu32h_T[2], ft); |
| 6258 | - gen_op_float_rsqrt2_ps(); | 6259 | + tcg_gen_helper_0_0(do_float_rsqrt2_ps); |
| 6259 | gen_store_fpr32(fpu32_T[2], fd); | 6260 | gen_store_fpr32(fpu32_T[2], fd); |
| 6260 | gen_store_fpr32h(fpu32h_T[2], fd); | 6261 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6261 | opn = "rsqrt2.ps"; | 6262 | opn = "rsqrt2.ps"; |
| @@ -6263,7 +6264,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6263,7 +6264,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6263 | case FOP(32, 22): | 6264 | case FOP(32, 22): |
| 6264 | check_cp1_64bitmode(ctx); | 6265 | check_cp1_64bitmode(ctx); |
| 6265 | gen_load_fpr32h(fpu32h_T[0], fs); | 6266 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6266 | - gen_op_float_cvts_pu(); | 6267 | + tcg_gen_helper_0_0(do_float_cvts_pu); |
| 6267 | gen_store_fpr32(fpu32_T[2], fd); | 6268 | gen_store_fpr32(fpu32_T[2], fd); |
| 6268 | opn = "cvt.s.pu"; | 6269 | opn = "cvt.s.pu"; |
| 6269 | break; | 6270 | break; |
| @@ -6271,7 +6272,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6271,7 +6272,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6271 | check_cp1_64bitmode(ctx); | 6272 | check_cp1_64bitmode(ctx); |
| 6272 | gen_load_fpr32(fpu32_T[0], fs); | 6273 | gen_load_fpr32(fpu32_T[0], fs); |
| 6273 | gen_load_fpr32h(fpu32h_T[0], fs); | 6274 | gen_load_fpr32h(fpu32h_T[0], fs); |
| 6274 | - gen_op_float_cvtpw_ps(); | 6275 | + tcg_gen_helper_0_0(do_float_cvtpw_ps); |
| 6275 | gen_store_fpr32(fpu32_T[2], fd); | 6276 | gen_store_fpr32(fpu32_T[2], fd); |
| 6276 | gen_store_fpr32h(fpu32h_T[2], fd); | 6277 | gen_store_fpr32h(fpu32h_T[2], fd); |
| 6277 | opn = "cvt.pw.ps"; | 6278 | opn = "cvt.pw.ps"; |
| @@ -6279,7 +6280,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | @@ -6279,7 +6280,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, | ||
| 6279 | case FOP(40, 22): | 6280 | case FOP(40, 22): |
| 6280 | check_cp1_64bitmode(ctx); | 6281 | check_cp1_64bitmode(ctx); |
| 6281 | gen_load_fpr32(fpu32_T[0], fs); | 6282 | gen_load_fpr32(fpu32_T[0], fs); |
| 6282 | - gen_op_float_cvts_pl(); | 6283 | + tcg_gen_helper_0_0(do_float_cvts_pl); |
| 6283 | gen_store_fpr32(fpu32_T[2], fd); | 6284 | gen_store_fpr32(fpu32_T[2], fd); |
| 6284 | opn = "cvt.s.pl"; | 6285 | opn = "cvt.s.pl"; |
| 6285 | break; | 6286 | break; |