Commit 5cc1d1e628f37424f2c96c585477aaf79ce0d9cc
1 parent
33c263df
save more CPU state
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4669 c046a42c-6fe2-441c-8c8c-71466251a162
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3 changed files
with
39 additions
and
7 deletions
hw/pc.c
... | ... | @@ -766,7 +766,7 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size, |
766 | 766 | /* XXX: enable it in all cases */ |
767 | 767 | env->cpuid_features |= CPUID_APIC; |
768 | 768 | } |
769 | - register_savevm("cpu", i, 4, cpu_save, cpu_load, env); | |
769 | + register_savevm("cpu", i, 5, cpu_save, cpu_load, env); | |
770 | 770 | qemu_register_reset(main_cpu_reset, env); |
771 | 771 | if (pci_enabled) { |
772 | 772 | apic_init(env); | ... | ... |
target-i386/cpu.h
... | ... | @@ -541,8 +541,8 @@ typedef struct CPUX86State { |
541 | 541 | uint64_t efer; |
542 | 542 | uint64_t star; |
543 | 543 | |
544 | - target_phys_addr_t vm_hsave; | |
545 | - target_phys_addr_t vm_vmcb; | |
544 | + uint64_t vm_hsave; | |
545 | + uint64_t vm_vmcb; | |
546 | 546 | uint64_t tsc_offset; |
547 | 547 | uint64_t intercept; |
548 | 548 | uint16_t intercept_cr_read; | ... | ... |
target-i386/machine.c
... | ... | @@ -120,6 +120,21 @@ void cpu_save(QEMUFile *f, void *opaque) |
120 | 120 | qemu_put_be64s(f, &env->kernelgsbase); |
121 | 121 | #endif |
122 | 122 | qemu_put_be32s(f, &env->smbase); |
123 | + | |
124 | + qemu_put_be64s(f, &env->pat); | |
125 | + qemu_put_be32s(f, &env->hflags2); | |
126 | + qemu_put_be32s(f, (uint32_t *)&env->halted); | |
127 | + | |
128 | + qemu_put_be64s(f, &env->vm_hsave); | |
129 | + qemu_put_be64s(f, &env->vm_vmcb); | |
130 | + qemu_put_be64s(f, &env->tsc_offset); | |
131 | + qemu_put_be64s(f, &env->intercept); | |
132 | + qemu_put_be16s(f, &env->intercept_cr_read); | |
133 | + qemu_put_be16s(f, &env->intercept_cr_write); | |
134 | + qemu_put_be16s(f, &env->intercept_dr_read); | |
135 | + qemu_put_be16s(f, &env->intercept_dr_write); | |
136 | + qemu_put_be32s(f, &env->intercept_exceptions); | |
137 | + qemu_put_8s(f, &env->v_tpr); | |
123 | 138 | } |
124 | 139 | |
125 | 140 | #ifdef USE_X86LDOUBLE |
... | ... | @@ -154,7 +169,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) |
154 | 169 | uint16_t fpus, fpuc, fptag, fpregs_format; |
155 | 170 | int32_t a20_mask; |
156 | 171 | |
157 | - if (version_id != 3 && version_id != 4) | |
172 | + if (version_id != 3 && version_id != 4 && version_id != 5) | |
158 | 173 | return -EINVAL; |
159 | 174 | for(i = 0; i < CPU_NB_REGS; i++) |
160 | 175 | qemu_get_betls(f, &env->regs[i]); |
... | ... | @@ -258,10 +273,27 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) |
258 | 273 | qemu_get_be64s(f, &env->fmask); |
259 | 274 | qemu_get_be64s(f, &env->kernelgsbase); |
260 | 275 | #endif |
261 | - if (version_id >= 4) | |
276 | + if (version_id >= 4) { | |
262 | 277 | qemu_get_be32s(f, &env->smbase); |
263 | - | |
264 | - /* XXX: compute hflags from scratch, except for CPL and IIF */ | |
278 | + } | |
279 | + if (version_id >= 5) { | |
280 | + qemu_get_be64s(f, &env->pat); | |
281 | + qemu_get_be32s(f, &env->hflags2); | |
282 | + qemu_get_be32s(f, (uint32_t *)&env->halted); | |
283 | + | |
284 | + qemu_get_be64s(f, &env->vm_hsave); | |
285 | + qemu_get_be64s(f, &env->vm_vmcb); | |
286 | + qemu_get_be64s(f, &env->tsc_offset); | |
287 | + qemu_get_be64s(f, &env->intercept); | |
288 | + qemu_get_be16s(f, &env->intercept_cr_read); | |
289 | + qemu_get_be16s(f, &env->intercept_cr_write); | |
290 | + qemu_get_be16s(f, &env->intercept_dr_read); | |
291 | + qemu_get_be16s(f, &env->intercept_dr_write); | |
292 | + qemu_get_be32s(f, &env->intercept_exceptions); | |
293 | + qemu_get_8s(f, &env->v_tpr); | |
294 | + } | |
295 | + /* XXX: ensure compatiblity for halted bit ? */ | |
296 | + /* XXX: compute redundant hflags bits */ | |
265 | 297 | env->hflags = hflags; |
266 | 298 | tlb_flush(env, 1); |
267 | 299 | return 0; | ... | ... |