Commit 5c2b87e34df1f00d8bb788b01a7506351421c10e
1 parent
567daa49
PIIX4 support, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2317 c046a42c-6fe2-441c-8c8c-71466251a162
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hw/piix_pci.c
| @@ -197,6 +197,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state) | @@ -197,6 +197,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state) | ||
| 197 | /* PIIX3 PCI to ISA bridge */ | 197 | /* PIIX3 PCI to ISA bridge */ |
| 198 | 198 | ||
| 199 | PCIDevice *piix3_dev; | 199 | PCIDevice *piix3_dev; |
| 200 | +PCIDevice *piix4_dev; | ||
| 200 | 201 | ||
| 201 | /* just used for simpler irq handling. */ | 202 | /* just used for simpler irq handling. */ |
| 202 | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) | 203 | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
| @@ -259,6 +260,44 @@ static void piix3_reset(PCIDevice *d) | @@ -259,6 +260,44 @@ static void piix3_reset(PCIDevice *d) | ||
| 259 | pci_conf[0xae] = 0x00; | 260 | pci_conf[0xae] = 0x00; |
| 260 | } | 261 | } |
| 261 | 262 | ||
| 263 | +static void piix4_reset(PCIDevice *d) | ||
| 264 | +{ | ||
| 265 | + uint8_t *pci_conf = d->config; | ||
| 266 | + | ||
| 267 | + pci_conf[0x04] = 0x07; // master, memory and I/O | ||
| 268 | + pci_conf[0x05] = 0x00; | ||
| 269 | + pci_conf[0x06] = 0x00; | ||
| 270 | + pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | ||
| 271 | + pci_conf[0x4c] = 0x4d; | ||
| 272 | + pci_conf[0x4e] = 0x03; | ||
| 273 | + pci_conf[0x4f] = 0x00; | ||
| 274 | + pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 | ||
| 275 | + pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 | ||
| 276 | + pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 | ||
| 277 | + pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 | ||
| 278 | + pci_conf[0x69] = 0x02; | ||
| 279 | + pci_conf[0x70] = 0x80; | ||
| 280 | + pci_conf[0x76] = 0x0c; | ||
| 281 | + pci_conf[0x77] = 0x0c; | ||
| 282 | + pci_conf[0x78] = 0x02; | ||
| 283 | + pci_conf[0x79] = 0x00; | ||
| 284 | + pci_conf[0x80] = 0x00; | ||
| 285 | + pci_conf[0x82] = 0x00; | ||
| 286 | + pci_conf[0xa0] = 0x08; | ||
| 287 | + pci_conf[0xa0] = 0x08; | ||
| 288 | + pci_conf[0xa2] = 0x00; | ||
| 289 | + pci_conf[0xa3] = 0x00; | ||
| 290 | + pci_conf[0xa4] = 0x00; | ||
| 291 | + pci_conf[0xa5] = 0x00; | ||
| 292 | + pci_conf[0xa6] = 0x00; | ||
| 293 | + pci_conf[0xa7] = 0x00; | ||
| 294 | + pci_conf[0xa8] = 0x0f; | ||
| 295 | + pci_conf[0xaa] = 0x00; | ||
| 296 | + pci_conf[0xab] = 0x00; | ||
| 297 | + pci_conf[0xac] = 0x00; | ||
| 298 | + pci_conf[0xae] = 0x00; | ||
| 299 | +} | ||
| 300 | + | ||
| 262 | static void piix_save(QEMUFile* f, void *opaque) | 301 | static void piix_save(QEMUFile* f, void *opaque) |
| 263 | { | 302 | { |
| 264 | PCIDevice *d = opaque; | 303 | PCIDevice *d = opaque; |
| @@ -296,3 +335,27 @@ int piix3_init(PCIBus *bus, int devfn) | @@ -296,3 +335,27 @@ int piix3_init(PCIBus *bus, int devfn) | ||
| 296 | piix3_reset(d); | 335 | piix3_reset(d); |
| 297 | return d->devfn; | 336 | return d->devfn; |
| 298 | } | 337 | } |
| 338 | + | ||
| 339 | +int piix4_init(PCIBus *bus, int devfn) | ||
| 340 | +{ | ||
| 341 | + PCIDevice *d; | ||
| 342 | + uint8_t *pci_conf; | ||
| 343 | + | ||
| 344 | + d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice), | ||
| 345 | + devfn, NULL, NULL); | ||
| 346 | + register_savevm("PIIX4", 0, 2, piix_save, piix_load, d); | ||
| 347 | + | ||
| 348 | + piix4_dev = d; | ||
| 349 | + pci_conf = d->config; | ||
| 350 | + | ||
| 351 | + pci_conf[0x00] = 0x86; // Intel | ||
| 352 | + pci_conf[0x01] = 0x80; | ||
| 353 | + pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge | ||
| 354 | + pci_conf[0x03] = 0x71; | ||
| 355 | + pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA | ||
| 356 | + pci_conf[0x0b] = 0x06; // class_base = PCI_bridge | ||
| 357 | + pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic | ||
| 358 | + | ||
| 359 | + piix4_reset(d); | ||
| 360 | + return d->devfn; | ||
| 361 | +} |