gwj / at91sam9263 · Commits

Commit 5b7141a11e2ef24caf26af95e59b2ed9552daa0e

Authored by aurel32
1 parent 1b6e5f99

sh4: Add FMAC instruction support 

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6309 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 23 additions and 0 deletions
target-sh4/helper.h
  View file @5b7141a
@@ -35,6 +35,7 @@ DEF_HELPER_2(fdiv_FT, i32, i32, i32) @@ -35,6 +35,7 @@ DEF_HELPER_2(fdiv_FT, i32, i32, i32)
35 DEF_HELPER_2(fdiv_DT, i64, i64, i64) 35 DEF_HELPER_2(fdiv_DT, i64, i64, i64)
36 DEF_HELPER_1(float_FT, i32, i32) 36 DEF_HELPER_1(float_FT, i32, i32)
37 DEF_HELPER_1(float_DT, i64, i32) 37 DEF_HELPER_1(float_DT, i64, i32)
  38 +DEF_HELPER_3(fmac_FT, i32, i32, i32, i32)
38 DEF_HELPER_2(fmul_FT, i32, i32, i32) 39 DEF_HELPER_2(fmul_FT, i32, i32, i32)
39 DEF_HELPER_2(fmul_DT, i64, i64, i64) 40 DEF_HELPER_2(fmul_DT, i64, i64, i64)
40 DEF_HELPER_1(fneg_T, i32, i32) 41 DEF_HELPER_1(fneg_T, i32, i32)
target-sh4/op_helper.c
  View file @5b7141a
@@ -531,6 +531,17 @@ uint64_t helper_float_DT(uint32_t t0) @@ -531,6 +531,17 @@ uint64_t helper_float_DT(uint32_t t0)
531 return d.ll; 531 return d.ll;
532 } 532 }
533 533
  534 +uint32_t helper_fmac_FT(uint32_t t0, uint32_t t1, uint32_t t2)
  535 +{
  536 + CPU_FloatU f0, f1, f2;
  537 + f0.l = t0;
  538 + f1.l = t1;
  539 + f2.l = t2;
  540 + f0.f = float32_mul(f0.f, f1.f, &env->fp_status);
  541 + f0.f = float32_add(f0.f, f2.f, &env->fp_status);
  542 + return f0.l;
  543 +}
  544 +
534 uint32_t helper_fmul_FT(uint32_t t0, uint32_t t1) 545 uint32_t helper_fmul_FT(uint32_t t0, uint32_t t1)
535 { 546 {
536 CPU_FloatU f0, f1; 547 CPU_FloatU f0, f1;
target-sh4/translate.c
  View file @5b7141a
@@ -1176,6 +1176,17 @@ static void _decode_opc(DisasContext * ctx) @@ -1176,6 +1176,17 @@ static void _decode_opc(DisasContext * ctx)
1176 } 1176 }
1177 } 1177 }
1178 return; 1178 return;
  1179 + case 0xf00e: /* fmac FR0,RM,Rn */
  1180 + {
  1181 + CHECK_FPU_ENABLED
  1182 + if (ctx->fpscr & FPSCR_PR) {
  1183 + break; /* illegal instruction */
  1184 + } else {
  1185 + gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
  1186 + cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
  1187 + return;
  1188 + }
  1189 + }
1179 } 1190 }
1180 1191
1181 switch (ctx->opcode & 0xff00) { 1192 switch (ctx->opcode & 0xff00) {