gwj / at91sam9263 · Commits

Commit 5ad6bb97a4a1fa2f230a28f83b7b8ed85de81c22

Authored by blueswir1
1 parent 2d8ee4e7

Name the magic constants, wrap long lines 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3751 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 135 additions and 85 deletions
hw/esp.c
  View file @5ad6bb9
... ... @@ -32,8 +32,8 @@
32 32 //#define DEBUG_ESP
33 33  
34 34 /*
35   - * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
36   - * produced as NCR89C100. See
  35 + * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  36 + * also produced as NCR89C100. See
37 37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
38 38 * and
39 39 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
... ... @@ -81,12 +81,51 @@ struct ESPState {
81 81 void *dma_opaque;
82 82 };
83 83  
  84 +#define ESP_TCLO 0x0
  85 +#define ESP_TCMID 0x1
  86 +#define ESP_FIFO 0x2
  87 +#define ESP_CMD 0x3
  88 +#define ESP_RSTAT 0x4
  89 +#define ESP_WBUSID 0x4
  90 +#define ESP_RINTR 0x5
  91 +#define ESP_WSEL 0x5
  92 +#define ESP_RSEQ 0x6
  93 +#define ESP_WSYNTP 0x6
  94 +#define ESP_RFLAGS 0x7
  95 +#define ESP_WSYNO 0x7
  96 +#define ESP_CFG1 0x8
  97 +#define ESP_RRES1 0x9
  98 +#define ESP_WCCF 0x9
  99 +#define ESP_RRES2 0xa
  100 +#define ESP_WTEST 0xa
  101 +#define ESP_CFG2 0xb
  102 +#define ESP_CFG3 0xc
  103 +#define ESP_RES3 0xd
  104 +#define ESP_TCHI 0xe
  105 +#define ESP_RES4 0xf
  106 +
  107 +#define CMD_DMA 0x80
  108 +#define CMD_CMD 0x7f
  109 +
  110 +#define CMD_NOP 0x00
  111 +#define CMD_FLUSH 0x01
  112 +#define CMD_RESET 0x02
  113 +#define CMD_BUSRESET 0x03
  114 +#define CMD_TI 0x10
  115 +#define CMD_ICCS 0x11
  116 +#define CMD_MSGACC 0x12
  117 +#define CMD_SATN 0x1a
  118 +#define CMD_SELATN 0x42
  119 +#define CMD_SELATNS 0x43
  120 +#define CMD_ENSEL 0x44
  121 +
84 122 #define STAT_DO 0x00
85 123 #define STAT_DI 0x01
86 124 #define STAT_CD 0x02
87 125 #define STAT_ST 0x03
88 126 #define STAT_MI 0x06
89 127 #define STAT_MO 0x07
  128 +#define STAT_PIO_MASK 0x06
90 129  
91 130 #define STAT_TC 0x10
92 131 #define STAT_PE 0x20
... ... @@ -101,13 +140,19 @@ struct ESPState {
101 140 #define SEQ_0 0x0
102 141 #define SEQ_CD 0x4
103 142  
  143 +#define CFG1_RESREPT 0x40
  144 +
  145 +#define CFG2_MASK 0x15
  146 +
  147 +#define TCHI_FAS100A 0x4
  148 +
104 149 static int get_cmd(ESPState *s, uint8_t *buf)
105 150 {
106 151 uint32_t dmalen;
107 152 int target;
108 153  
109   - dmalen = s->rregs[0] | (s->rregs[1] << 8);
110   - target = s->wregs[4] & 7;
  154 + dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
  155 + target = s->wregs[ESP_WBUSID] & 7;
111 156 DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
112 157 if (s->dma) {
113 158 espdma_memory_read(s->dma_opaque, buf, dmalen);
... ... @@ -129,9 +174,9 @@ static int get_cmd(ESPState *s, uint8_t *buf)
129 174  
130 175 if (target >= MAX_DISKS || !s->scsi_dev[target]) {
131 176 // No such drive
132   - s->rregs[4] = STAT_IN;
133   - s->rregs[5] = INTR_DC;
134   - s->rregs[6] = SEQ_0;
  177 + s->rregs[ESP_RSTAT] = STAT_IN;
  178 + s->rregs[ESP_RINTR] = INTR_DC;
  179 + s->rregs[ESP_RSEQ] = SEQ_0;
135 180 qemu_irq_raise(s->irq);
136 181 return 0;
137 182 }
... ... @@ -149,19 +194,19 @@ static void do_cmd(ESPState *s, uint8_t *buf)
149 194 datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
150 195 s->ti_size = datalen;
151 196 if (datalen != 0) {
152   - s->rregs[4] = STAT_IN | STAT_TC;
  197 + s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC;
153 198 s->dma_left = 0;
154 199 s->dma_counter = 0;
155 200 if (datalen > 0) {
156   - s->rregs[4] |= STAT_DI;
  201 + s->rregs[ESP_RSTAT] |= STAT_DI;
157 202 scsi_read_data(s->current_dev, 0);
158 203 } else {
159   - s->rregs[4] |= STAT_DO;
  204 + s->rregs[ESP_RSTAT] |= STAT_DO;
160 205 scsi_write_data(s->current_dev, 0);
161 206 }
162 207 }
163   - s->rregs[5] = INTR_BS | INTR_FC;
164   - s->rregs[6] = SEQ_CD;
  208 + s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
  209 + s->rregs[ESP_RSEQ] = SEQ_CD;
165 210 qemu_irq_raise(s->irq);
166 211 }
167 212  
... ... @@ -181,9 +226,9 @@ static void handle_satn_stop(ESPState *s)
181 226 if (s->cmdlen) {
182 227 DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
183 228 s->do_cmd = 1;
184   - s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
185   - s->rregs[5] = INTR_BS | INTR_FC;
186   - s->rregs[6] = SEQ_CD;
  229 + s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_CD;
  230 + s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
  231 + s->rregs[ESP_RSEQ] = SEQ_CD;
187 232 qemu_irq_raise(s->irq);
188 233 }
189 234 }
... ... @@ -195,26 +240,26 @@ static void write_response(ESPState *s)
195 240 s->ti_buf[1] = 0;
196 241 if (s->dma) {
197 242 espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
198   - s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
199   - s->rregs[5] = INTR_BS | INTR_FC;
200   - s->rregs[6] = SEQ_CD;
  243 + s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_ST;
  244 + s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
  245 + s->rregs[ESP_RSEQ] = SEQ_CD;
201 246 } else {
202 247 s->ti_size = 2;
203 248 s->ti_rptr = 0;
204 249 s->ti_wptr = 0;
205   - s->rregs[7] = 2;
  250 + s->rregs[ESP_RFLAGS] = 2;
206 251 }
207 252 qemu_irq_raise(s->irq);
208 253 }
209 254  
210 255 static void esp_dma_done(ESPState *s)
211 256 {
212   - s->rregs[4] |= STAT_IN | STAT_TC;
213   - s->rregs[5] = INTR_BS;
214   - s->rregs[6] = 0;
215   - s->rregs[7] = 0;
216   - s->rregs[0] = 0;
217   - s->rregs[1] = 0;
  257 + s->rregs[ESP_RSTAT] |= STAT_IN | STAT_TC;
  258 + s->rregs[ESP_RINTR] = INTR_BS;
  259 + s->rregs[ESP_RSEQ] = 0;
  260 + s->rregs[ESP_RFLAGS] = 0;
  261 + s->rregs[ESP_TCLO] = 0;
  262 + s->rregs[ESP_TCMID] = 0;
218 263 qemu_irq_raise(s->irq);
219 264 }
220 265  
... ... @@ -287,7 +332,7 @@ static void esp_command_complete(void *opaque, int reason, uint32_t tag,
287 332 if (arg)
288 333 DPRINTF("Command failed\n");
289 334 s->sense = arg;
290   - s->rregs[4] = STAT_ST;
  335 + s->rregs[ESP_RSTAT] = STAT_ST;
291 336 esp_dma_done(s);
292 337 s->current_dev = NULL;
293 338 } else {
... ... @@ -308,7 +353,7 @@ static void handle_ti(ESPState *s)
308 353 {
309 354 uint32_t dmalen, minlen;
310 355  
311   - dmalen = s->rregs[0] | (s->rregs[1] << 8);
  356 + dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
312 357 if (dmalen==0) {
313 358 dmalen=0x10000;
314 359 }
... ... @@ -323,7 +368,7 @@ static void handle_ti(ESPState *s)
323 368 DPRINTF("Transfer Information len %d\n", minlen);
324 369 if (s->dma) {
325 370 s->dma_left = minlen;
326   - s->rregs[4] &= ~STAT_TC;
  371 + s->rregs[ESP_RSTAT] &= ~STAT_TC;
327 372 esp_do_dma(s);
328 373 } else if (s->do_cmd) {
329 374 DPRINTF("command len %d\n", s->cmdlen);
... ... @@ -341,7 +386,7 @@ static void esp_reset(void *opaque)
341 386  
342 387 memset(s->rregs, 0, ESP_REGS);
343 388 memset(s->wregs, 0, ESP_REGS);
344   - s->rregs[0x0e] = 0x4; // Indicate fas100a
  389 + s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
345 390 s->ti_size = 0;
346 391 s->ti_rptr = 0;
347 392 s->ti_wptr = 0;
... ... @@ -363,16 +408,15 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
363 408 saddr = (addr & ESP_MASK) >> 2;
364 409 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
365 410 switch (saddr) {
366   - case 2:
367   - // FIFO
  411 + case ESP_FIFO:
368 412 if (s->ti_size > 0) {
369 413 s->ti_size--;
370   - if ((s->rregs[4] & 6) == 0) {
  414 + if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
371 415 /* Data in/out. */
372 416 fprintf(stderr, "esp: PIO data read not implemented\n");
373   - s->rregs[2] = 0;
  417 + s->rregs[ESP_FIFO] = 0;
374 418 } else {
375   - s->rregs[2] = s->ti_buf[s->ti_rptr++];
  419 + s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
376 420 }
377 421 qemu_irq_raise(s->irq);
378 422 }
... ... @@ -381,10 +425,9 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
381 425 s->ti_wptr = 0;
382 426 }
383 427 break;
384   - case 5:
385   - // interrupt
  428 + case ESP_RINTR:
386 429 // Clear interrupt/error status bits
387   - s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
  430 + s->rregs[ESP_RSTAT] &= ~(STAT_IN | STAT_GE | STAT_PE);
388 431 qemu_irq_lower(s->irq);
389 432 break;
390 433 default:
... ... @@ -399,17 +442,17 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
399 442 uint32_t saddr;
400 443  
401 444 saddr = (addr & ESP_MASK) >> 2;
402   - DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
  445 + DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
  446 + val);
403 447 switch (saddr) {
404   - case 0:
405   - case 1:
406   - s->rregs[4] &= ~STAT_TC;
  448 + case ESP_TCLO:
  449 + case ESP_TCMID:
  450 + s->rregs[ESP_RSTAT] &= ~STAT_TC;
407 451 break;
408   - case 2:
409   - // FIFO
  452 + case ESP_FIFO:
410 453 if (s->do_cmd) {
411 454 s->cmdbuf[s->cmdlen++] = val & 0xff;
412   - } else if ((s->rregs[4] & 6) == 0) {
  455 + } else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
413 456 uint8_t buf;
414 457 buf = val & 0xff;
415 458 s->ti_size--;
... ... @@ -419,63 +462,62 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
419 462 s->ti_buf[s->ti_wptr++] = val & 0xff;
420 463 }
421 464 break;
422   - case 3:
  465 + case ESP_CMD:
423 466 s->rregs[saddr] = val;
424   - // Command
425   - if (val & 0x80) {
  467 + if (val & CMD_DMA) {
426 468 s->dma = 1;
427 469 /* Reload DMA counter. */
428   - s->rregs[0] = s->wregs[0];
429   - s->rregs[1] = s->wregs[1];
  470 + s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
  471 + s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
430 472 } else {
431 473 s->dma = 0;
432 474 }
433   - switch(val & 0x7f) {
434   - case 0:
  475 + switch(val & CMD_CMD) {
  476 + case CMD_NOP:
435 477 DPRINTF("NOP (%2.2x)\n", val);
436 478 break;
437   - case 1:
  479 + case CMD_FLUSH:
438 480 DPRINTF("Flush FIFO (%2.2x)\n", val);
439 481 //s->ti_size = 0;
440   - s->rregs[5] = INTR_FC;
441   - s->rregs[6] = 0;
  482 + s->rregs[ESP_RINTR] = INTR_FC;
  483 + s->rregs[ESP_RSEQ] = 0;
442 484 break;
443   - case 2:
  485 + case CMD_RESET:
444 486 DPRINTF("Chip reset (%2.2x)\n", val);
445 487 esp_reset(s);
446 488 break;
447   - case 3:
  489 + case CMD_BUSRESET:
448 490 DPRINTF("Bus reset (%2.2x)\n", val);
449   - s->rregs[5] = INTR_RST;
450   - if (!(s->wregs[8] & 0x40)) {
  491 + s->rregs[ESP_RINTR] = INTR_RST;
  492 + if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
451 493 qemu_irq_raise(s->irq);
452 494 }
453 495 break;
454   - case 0x10:
  496 + case CMD_TI:
455 497 handle_ti(s);
456 498 break;
457   - case 0x11:
  499 + case CMD_ICCS:
458 500 DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
459 501 write_response(s);
460 502 break;
461   - case 0x12:
  503 + case CMD_MSGACC:
462 504 DPRINTF("Message Accepted (%2.2x)\n", val);
463 505 write_response(s);
464   - s->rregs[5] = INTR_DC;
465   - s->rregs[6] = 0;
  506 + s->rregs[ESP_RINTR] = INTR_DC;
  507 + s->rregs[ESP_RSEQ] = 0;
466 508 break;
467   - case 0x1a:
  509 + case CMD_SATN:
468 510 DPRINTF("Set ATN (%2.2x)\n", val);
469 511 break;
470   - case 0x42:
  512 + case CMD_SELATN:
471 513 DPRINTF("Set ATN (%2.2x)\n", val);
472 514 handle_satn(s);
473 515 break;
474   - case 0x43:
  516 + case CMD_SELATNS:
475 517 DPRINTF("Set ATN & stop (%2.2x)\n", val);
476 518 handle_satn_stop(s);
477 519 break;
478   - case 0x44:
  520 + case CMD_ENSEL:
479 521 DPRINTF("Enable selection (%2.2x)\n", val);
480 522 break;
481 523 default:
... ... @@ -483,17 +525,17 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
483 525 break;
484 526 }
485 527 break;
486   - case 4 ... 7:
  528 + case ESP_WBUSID ... ESP_WSYNO:
487 529 break;
488   - case 8:
  530 + case ESP_CFG1:
489 531 s->rregs[saddr] = val;
490 532 break;
491   - case 9 ... 10:
  533 + case ESP_WCCF ... ESP_WTEST:
492 534 break;
493   - case 11:
494   - s->rregs[saddr] = val & 0x15;
  535 + case ESP_CFG2:
  536 + s->rregs[saddr] = val & CFG2_MASK;
495 537 break;
496   - case 12 ... 15:
  538 + case ESP_CFG3 ... ESP_RES4:
497 539 s->rregs[saddr] = val;
498 540 break;
499 541 default:
... ...
hw/iommu.c
  View file @5ad6bb9
... ... @@ -61,12 +61,16 @@ do { printf(&quot;IOMMU: &quot; fmt , ##args); } while (0)
61 61  
62 62 #define IOMMU_AFSR (0x1000 >> 2)
63 63 #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
64   -#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
65   -#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
66   -#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
  64 +#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
  65 + transaction */
  66 +#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
  67 + 12.8 us. */
  68 +#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
  69 + acknowledge */
67 70 #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
68 71 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
69   -#define IOMMU_AFSR_RESV 0x00f00000 /* Reserved, forced to 0x8 by hardware */
  72 +#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
  73 + hardware */
70 74 #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
71 75 #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
72 76 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
... ... @@ -77,7 +81,8 @@ do { printf(&quot;IOMMU: &quot; fmt , ##args); } while (0)
77 81 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
78 82 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
79 83 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
80   -#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
  84 +#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
  85 + bypass enabled */
81 86 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
82 87 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
83 88 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
... ... @@ -91,7 +96,8 @@ do { printf(&quot;IOMMU: &quot; fmt , ##args); } while (0)
91 96  
92 97 /* The format of an iopte in the page tables */
93 98 #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
94   -#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
  99 +#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
  100 + Viking/MXCC) */
95 101 #define IOPTE_WRITE 0x00000004 /* Writeable */
96 102 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
97 103 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
... ... @@ -122,7 +128,8 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
122 128 return 0;
123 129 }
124 130  
125   -static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
  131 +static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
  132 + uint32_t val)
126 133 {
127 134 IOMMUState *s = opaque;
128 135 target_phys_addr_t saddr;
... ... @@ -235,10 +242,11 @@ static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
235 242 return pa;
236 243 }
237 244  
238   -static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write)
  245 +static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
  246 + int is_write)
239 247 {
240 248 DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
241   - s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | (8 << 20) |
  249 + s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
242 250 IOMMU_AFSR_FAV;
243 251 if (!is_write)
244 252 s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
... ... @@ -311,7 +319,7 @@ static void iommu_reset(void *opaque)
311 319 s->iostart = 0;
312 320 s->regs[IOMMU_CTRL] = s->version;
313 321 s->regs[IOMMU_ARBEN] = IOMMU_MID;
314   - s->regs[IOMMU_AFSR] = 0x00800000;
  322 + s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
315 323 }
316 324  
317 325 void *iommu_init(target_phys_addr_t addr, uint32_t version)
... ... @@ -326,7 +334,8 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version)
326 334 s->addr = addr;
327 335 s->version = version;
328 336  
329   - iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
  337 + iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
  338 + iommu_mem_write, s);
330 339 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
331 340  
332 341 register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
... ... @@ -334,4 +343,3 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version)
334 343 iommu_reset(s);
335 344 return s;
336 345 }
337   -
... ...