gwj / at91sam9263 · Commits

Commit 59d9413094d7295d74926e63d7df4963399ab53a

Authored by aurel32
1 parent 0516ede0

target-mips: CP0 Random register improvements 

- Use a LFSR to generate the random value
- Make sure to not return the same value twice

Based on a patch by Hervé Poussineau.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6233 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 8 additions and 3 deletions
hw/mips_timer.c
  View file @59d9413
... ... @@ -7,10 +7,15 @@
7 7 /* XXX: do not use a global */
8 8 uint32_t cpu_mips_get_random (CPUState *env)
9 9 {
10   - static uint32_t seed = 0;
  10 + static uint32_t lfsr = 1;
  11 + static uint32_t prev_idx = 0;
11 12 uint32_t idx;
12   - seed = seed * 314159 + 1;
13   - idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
  13 + /* Don't return same value twice, so get another value */
  14 + do {
  15 + lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
  16 + idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
  17 + } while (idx == prev_idx);
  18 + prev_idx = idx;
14 19 return idx;
15 20 }
16 21  
... ...