Commit 57d69a91c41e71ae5f5181c6dedd62dc866234b5
1 parent
c7b76a0a
Force correct evaluation order in a a == b != c condition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4358 c046a42c-6fe2-441c-8c8c-71466251a162
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hw/arm_gic.c
| ... | ... | @@ -62,7 +62,7 @@ typedef struct gic_irq_state |
| 62 | 62 | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model |
| 63 | 63 | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) |
| 64 | 64 | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) |
| 65 | -#define GIC_TEST_LEVEL(irq, cm) (s->irq_state[irq].level & (cm)) != 0 | |
| 65 | +#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) | |
| 66 | 66 | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
| 67 | 67 | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
| 68 | 68 | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger | ... | ... |