gwj / at91sam9263 · Commits

Commit 57c26279c7bdef3cb181ea0afbd062a87d4ed6a0

Authored by j_mayer
1 parent d2fd1af7

Fix PowerPC targets compilation on 32 bits hosts: 

now that the SPE extension is available for all targets,
 we always need to have some 64 bits temporary registers.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 5 additions and 5 deletions
target-ppc/cpu.h
  View file @57c2627
@@ -520,11 +520,11 @@ struct CPUPPCState { @@ -520,11 +520,11 @@ struct CPUPPCState {
520 /* First are the most commonly used resources 520 /* First are the most commonly used resources
521 * during translated code execution 521 * during translated code execution
522 */ 522 */
523 -#if TARGET_GPR_BITS > HOST_LONG_BITS 523 +#if (HOST_LONG_BITS == 32)
524 /* temporary fixed-point registers 524 /* temporary fixed-point registers
525 - * used to emulate 64 bits target on 32 bits hosts 525 + * used to emulate 64 bits registers on 32 bits hosts
526 */ 526 */
527 - ppc_gpr_t t0, t1, t2; 527 + uint64_t t0, t1, t2;
528 #endif 528 #endif
529 ppc_avr_t avr0, avr1, avr2; 529 ppc_avr_t avr0, avr1, avr2;
530 530
target-ppc/exec.h
  View file @57c2627
@@ -42,8 +42,8 @@ register unsigned long T0 asm(AREG1); @@ -42,8 +42,8 @@ register unsigned long T0 asm(AREG1);
42 register unsigned long T1 asm(AREG2); 42 register unsigned long T1 asm(AREG2);
43 register unsigned long T2 asm(AREG3); 43 register unsigned long T2 asm(AREG3);
44 #endif 44 #endif
45 -/* We may, sometime, need 64 bits registers on 32 bits target */  
46 -#if TARGET_GPR_BITS > HOST_LONG_BITS 45 +/* We may, sometime, need 64 bits registers on 32 bits targets */
  46 +#if (HOST_LONG_BITS == 32)
47 /* no registers can be used */ 47 /* no registers can be used */
48 #define T0_64 (env->t0) 48 #define T0_64 (env->t0)
49 #define T1_64 (env->t1) 49 #define T1_64 (env->t1)