gwj / at91sam9263 · Commits

Commit 57a92c8e36ee9c0774d58c086b76b67ae981e6d4

Authored by aurel32
1 parent e32ad5c2

target-alpha: fix locked loads/stores 

Fix reading of cpu_lock in gen_qemu_stql_c, original patch from Laurent
Desnogues.

A new flag was added to gen_store_mem to allocate local temps instead
of temps;  this flag should be set when the tcg_gen_qemu_store callback
uses brcond before using the temps or else liveness analysis will get
rid of the temps.

This also adds lock printing in cpu_dump_state which can help
debug.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5645 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 22 additions and 13 deletions
target-alpha/helper.c
  View file @57a92c8
... ... @@ -434,5 +434,6 @@ void cpu_dump_state (CPUState *env, FILE *f,
434 434 if ((i % 3) == 2)
435 435 cpu_fprintf(f, "\n");
436 436 }
  437 + cpu_fprintf(f, "\nlock " TARGET_FMT_lx "\n", env->lock);
437 438 }
438 439  
... ...
target-alpha/translate.c
  View file @57a92c8
... ... @@ -234,9 +234,13 @@ static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
234 234 static always_inline void gen_store_mem (DisasContext *ctx,
235 235 void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
236 236 int ra, int rb, int32_t disp16,
237   - int fp, int clear)
  237 + int fp, int clear, int local)
238 238 {
239 239 TCGv addr = tcg_temp_new(TCG_TYPE_I64);
  240 + if (local)
  241 + addr = tcg_temp_local_new(TCG_TYPE_I64);
  242 + else
  243 + addr = tcg_temp_new(TCG_TYPE_I64);
240 244 if (rb != 31) {
241 245 tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
242 246 if (clear)
... ... @@ -252,7 +256,11 @@ static always_inline void gen_store_mem (DisasContext *ctx,
252 256 else
253 257 tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);
254 258 } else {
255   - TCGv zero = tcg_const_i64(0);
  259 + TCGv zero;
  260 + if (local)
  261 + zero = tcg_const_local_i64(0);
  262 + else
  263 + zero = tcg_const_i64(0);
256 264 tcg_gen_qemu_store(zero, addr, ctx->mem_idx);
257 265 tcg_temp_free(zero);
258 266 }
... ... @@ -636,15 +644,15 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
636 644 break;
637 645 case 0x0D:
638 646 /* STW */
639   - gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
  647 + gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0);
640 648 break;
641 649 case 0x0E:
642 650 /* STB */
643   - gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);
  651 + gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0);
644 652 break;
645 653 case 0x0F:
646 654 /* STQ_U */
647   - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1);
  655 + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0);
648 656 break;
649 657 case 0x10:
650 658 switch (fn7) {
... ... @@ -2090,19 +2098,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2090 2098 break;
2091 2099 case 0x24:
2092 2100 /* STF */
2093   - gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
  2101 + gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0);
2094 2102 break;
2095 2103 case 0x25:
2096 2104 /* STG */
2097   - gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
  2105 + gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0);
2098 2106 break;
2099 2107 case 0x26:
2100 2108 /* STS */
2101   - gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
  2109 + gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0);
2102 2110 break;
2103 2111 case 0x27:
2104 2112 /* STT */
2105   - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
  2113 + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0);
2106 2114 break;
2107 2115 case 0x28:
2108 2116 /* LDL */
... ... @@ -2122,19 +2130,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
2122 2130 break;
2123 2131 case 0x2C:
2124 2132 /* STL */
2125   - gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0);
  2133 + gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0);
2126 2134 break;
2127 2135 case 0x2D:
2128 2136 /* STQ */
2129   - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0);
  2137 + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0);
2130 2138 break;
2131 2139 case 0x2E:
2132 2140 /* STL_C */
2133   - gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0);
  2141 + gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1);
2134 2142 break;
2135 2143 case 0x2F:
2136 2144 /* STQ_C */
2137   - gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0);
  2145 + gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1);
2138 2146 break;
2139 2147 case 0x30:
2140 2148 /* BR */
... ...