gwj / at91sam9263 · Commits

Commit 56aebc891674cd2d07b3f64183415697be200084

Authored by pbrook
1 parent 1792f286

Add GDB XML register description support. 

Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 13 changed files with 1239 additions and 605 deletions
Makefile.target
  View file @56aebc8
... ... @@ -418,7 +418,7 @@ OBJS+= m68k-sim.o m68k-semi.o
418 418 endif
419 419  
420 420 ifdef CONFIG_GDBSTUB
421   -OBJS+=gdbstub.o
  421 +OBJS+=gdbstub.o gdbstub-xml.o
422 422 endif
423 423  
424 424 OBJS+= libqemu.a
... ... @@ -456,7 +456,7 @@ OBJS= main.o commpage.o machload.o mmap.o signal.o syscall.o thunk.o
456 456 OBJS+= libqemu.a
457 457  
458 458 ifdef CONFIG_GDBSTUB
459   -OBJS+=gdbstub.o
  459 +OBJS+=gdbstub.o gdbstub-xml.o
460 460 endif
461 461  
462 462 # Note: this is a workaround. The real fix is to avoid compiling
... ... @@ -626,7 +626,7 @@ OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
626 626 OBJS+= m68k-semi.o dummy_m68k.o
627 627 endif
628 628 ifdef CONFIG_GDBSTUB
629   -OBJS+=gdbstub.o
  629 +OBJS+=gdbstub.o gdbstub-xml.o
630 630 endif
631 631 ifdef CONFIG_COCOA
632 632 COCOA_LIBS=-F/System/Library/Frameworks -framework Cocoa -framework IOKit
... ... @@ -674,6 +674,14 @@ $(QEMU_PROG): $(OBJS) ../libqemu_common.a libqemu.a
674 674  
675 675 endif # !CONFIG_USER_ONLY
676 676  
  677 +gdbstub-xml.c: $(TARGET_XML_FILES) feature_to_c.sh
  678 + rm -f $@
  679 +ifeq ($(TARGET_XML_FILES),)
  680 + echo > $@
  681 +else
  682 + $(SHELL) $(SRC_PATH)/feature_to_c.sh $@ $(TARGET_XML_FILES)
  683 +endif
  684 +
677 685 %.o: %.c
678 686 $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<
679 687  
... ...
configure
  View file @56aebc8
... ... @@ -1386,6 +1386,7 @@ elfload32=&quot;no&quot;
1386 1386 target_nptl="no"
1387 1387 interp_prefix1=`echo "$interp_prefix" | sed "s/%M/$target_cpu/g"`
1388 1388 echo "#define CONFIG_QEMU_PREFIX \"$interp_prefix1\"" >> $config_h
  1389 +gdb_xml_files=""
1389 1390  
1390 1391 case "$target_cpu" in
1391 1392 i386)
... ... @@ -1425,6 +1426,7 @@ case &quot;$target_cpu&quot; in
1425 1426 echo "#define TARGET_ARM 1" >> $config_h
1426 1427 bflt="yes"
1427 1428 target_nptl="yes"
  1429 + gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"
1428 1430 ;;
1429 1431 cris)
1430 1432 echo "TARGET_ARCH=cris" >> $config_mak
... ... @@ -1436,6 +1438,7 @@ case &quot;$target_cpu&quot; in
1436 1438 echo "#define TARGET_ARCH \"m68k\"" >> $config_h
1437 1439 echo "#define TARGET_M68K 1" >> $config_h
1438 1440 bflt="yes"
  1441 + gdb_xml_files="cf-core.xml cf-fp.xml"
1439 1442 ;;
1440 1443 mips|mipsel)
1441 1444 echo "TARGET_ARCH=mips" >> $config_mak
... ... @@ -1545,6 +1548,13 @@ if test &quot;$target_darwin_user&quot; = &quot;yes&quot; ; then
1545 1548 echo "CONFIG_DARWIN_USER=yes" >> $config_mak
1546 1549 echo "#define CONFIG_DARWIN_USER 1" >> $config_h
1547 1550 fi
  1551 +list=""
  1552 +if test ! -z "$gdb_xml_files" ; then
  1553 + for x in $gdb_xml_files; do
  1554 + list="$list $source_path/gdb-xml/$x"
  1555 + done
  1556 +fi
  1557 +echo "TARGET_XML_FILES=$list" >> $config_mak
1548 1558  
1549 1559 if test "$target_cpu" = "arm" \
1550 1560 -o "$target_cpu" = "armeb" \
... ...
cpu-defs.h
  View file @56aebc8
... ... @@ -185,6 +185,8 @@ typedef struct icount_decr_u16 {
185 185 int nb_watchpoints; \
186 186 int watchpoint_hit; \
187 187 \
  188 + struct GDBRegisterState *gdb_regs; \
  189 + \
188 190 /* Core interrupt code */ \
189 191 jmp_buf jmp_env; \
190 192 int exception_index; \
... ...
gdb-xml/arm-core.xml 0 → 100644
  View file @56aebc8
  1 +<?xml version="1.0"?>
  2 +<!-- Copyright (C) 2008 Free Software Foundation, Inc.
  3 +
  4 + Copying and distribution of this file, with or without modification,
  5 + are permitted in any medium without royalty provided the copyright
  6 + notice and this notice are preserved. -->
  7 +
  8 +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
  9 +<feature name="org.gnu.gdb.arm.core">
  10 + <reg name="r0" bitsize="32"/>
  11 + <reg name="r1" bitsize="32"/>
  12 + <reg name="r2" bitsize="32"/>
  13 + <reg name="r3" bitsize="32"/>
  14 + <reg name="r4" bitsize="32"/>
  15 + <reg name="r5" bitsize="32"/>
  16 + <reg name="r6" bitsize="32"/>
  17 + <reg name="r7" bitsize="32"/>
  18 + <reg name="r8" bitsize="32"/>
  19 + <reg name="r9" bitsize="32"/>
  20 + <reg name="r10" bitsize="32"/>
  21 + <reg name="r11" bitsize="32"/>
  22 + <reg name="r12" bitsize="32"/>
  23 + <reg name="sp" bitsize="32" type="data_ptr"/>
  24 + <reg name="lr" bitsize="32"/>
  25 + <reg name="pc" bitsize="32" type="code_ptr"/>
  26 +
  27 + <!-- The CPSR is register 25, rather than register 16, because
  28 + the FPA registers historically were placed between the PC
  29 + and the CPSR in the "g" packet. -->
  30 + <reg name="cpsr" bitsize="32" regnum="25"/>
  31 +</feature>
... ...
gdb-xml/arm-neon.xml 0 → 100644
  View file @56aebc8
  1 +<?xml version="1.0"?>
  2 +<!-- Copyright (C) 2008 Free Software Foundation, Inc.
  3 +
  4 + Copying and distribution of this file, with or without modification,
  5 + are permitted in any medium without royalty provided the copyright
  6 + notice and this notice are preserved. -->
  7 +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
  8 +<feature name="org.gnu.gdb.arm.neon">
  9 + <vector id="neon_uint8x8" type="uint8" count="8"/>
  10 + <vector id="neon_uint16x4" type="uint16" count="4"/>
  11 + <vector id="neon_uint32x2" type="uint32" count="2"/>
  12 + <vector id="neon_float32x2" type="ieee_single" count="2"/>
  13 + <union id="neon_d">
  14 + <field name="u8" type="neon_uint8x8"/>
  15 + <field name="u16" type="neon_uint16x4"/>
  16 + <field name="u32" type="neon_uint32x2"/>
  17 + <field name="u64" type="uint64"/>
  18 + <field name="f32" type="neon_float32x2"/>
  19 + <field name="f64" type="ieee_double"/>
  20 + </union>
  21 + <vector id="neon_uint8x16" type="uint8" count="16"/>
  22 + <vector id="neon_uint16x8" type="uint16" count="8"/>
  23 + <vector id="neon_uint32x4" type="uint32" count="4"/>
  24 + <vector id="neon_uint64x2" type="uint64" count="2"/>
  25 + <vector id="neon_float32x4" type="ieee_single" count="4"/>
  26 + <vector id="neon_float64x2" type="ieee_double" count="2"/>
  27 + <union id="neon_q">
  28 + <field name="u8" type="neon_uint8x16"/>
  29 + <field name="u16" type="neon_uint16x8"/>
  30 + <field name="u32" type="neon_uint32x4"/>
  31 + <field name="u64" type="neon_uint64x2"/>
  32 + <field name="f32" type="neon_float32x4"/>
  33 + <field name="f64" type="neon_float64x2"/>
  34 + </union>
  35 + <reg name="d0" bitsize="64" type="neon_d"/>
  36 + <reg name="d1" bitsize="64" type="neon_d"/>
  37 + <reg name="d2" bitsize="64" type="neon_d"/>
  38 + <reg name="d3" bitsize="64" type="neon_d"/>
  39 + <reg name="d4" bitsize="64" type="neon_d"/>
  40 + <reg name="d5" bitsize="64" type="neon_d"/>
  41 + <reg name="d6" bitsize="64" type="neon_d"/>
  42 + <reg name="d7" bitsize="64" type="neon_d"/>
  43 + <reg name="d8" bitsize="64" type="neon_d"/>
  44 + <reg name="d9" bitsize="64" type="neon_d"/>
  45 + <reg name="d10" bitsize="64" type="neon_d"/>
  46 + <reg name="d11" bitsize="64" type="neon_d"/>
  47 + <reg name="d12" bitsize="64" type="neon_d"/>
  48 + <reg name="d13" bitsize="64" type="neon_d"/>
  49 + <reg name="d14" bitsize="64" type="neon_d"/>
  50 + <reg name="d15" bitsize="64" type="neon_d"/>
  51 + <reg name="d16" bitsize="64" type="neon_d"/>
  52 + <reg name="d17" bitsize="64" type="neon_d"/>
  53 + <reg name="d18" bitsize="64" type="neon_d"/>
  54 + <reg name="d19" bitsize="64" type="neon_d"/>
  55 + <reg name="d20" bitsize="64" type="neon_d"/>
  56 + <reg name="d21" bitsize="64" type="neon_d"/>
  57 + <reg name="d22" bitsize="64" type="neon_d"/>
  58 + <reg name="d23" bitsize="64" type="neon_d"/>
  59 + <reg name="d24" bitsize="64" type="neon_d"/>
  60 + <reg name="d25" bitsize="64" type="neon_d"/>
  61 + <reg name="d26" bitsize="64" type="neon_d"/>
  62 + <reg name="d27" bitsize="64" type="neon_d"/>
  63 + <reg name="d28" bitsize="64" type="neon_d"/>
  64 + <reg name="d29" bitsize="64" type="neon_d"/>
  65 + <reg name="d30" bitsize="64" type="neon_d"/>
  66 + <reg name="d31" bitsize="64" type="neon_d"/>
  67 +
  68 + <reg name="q0" bitsize="128" type="neon_q"/>
  69 + <reg name="q1" bitsize="128" type="neon_q"/>
  70 + <reg name="q2" bitsize="128" type="neon_q"/>
  71 + <reg name="q3" bitsize="128" type="neon_q"/>
  72 + <reg name="q4" bitsize="128" type="neon_q"/>
  73 + <reg name="q5" bitsize="128" type="neon_q"/>
  74 + <reg name="q6" bitsize="128" type="neon_q"/>
  75 + <reg name="q7" bitsize="128" type="neon_q"/>
  76 + <reg name="q8" bitsize="128" type="neon_q"/>
  77 + <reg name="q9" bitsize="128" type="neon_q"/>
  78 + <reg name="q10" bitsize="128" type="neon_q"/>
  79 + <reg name="q10" bitsize="128" type="neon_q"/>
  80 + <reg name="q12" bitsize="128" type="neon_q"/>
  81 + <reg name="q13" bitsize="128" type="neon_q"/>
  82 + <reg name="q14" bitsize="128" type="neon_q"/>
  83 + <reg name="q15" bitsize="128" type="neon_q"/>
  84 +
  85 + <reg name="fpsid" bitsize="32" type="int" group="float"/>
  86 + <reg name="fpscr" bitsize="32" type="int" group="float"/>
  87 + <reg name="fpexc" bitsize="32" type="int" group="float"/>
  88 +</feature>
... ...
gdb-xml/arm-vfp.xml 0 → 100644
  View file @56aebc8
  1 +<?xml version="1.0"?>
  2 +<!-- Copyright (C) 2008 Free Software Foundation, Inc.
  3 +
  4 + Copying and distribution of this file, with or without modification,
  5 + are permitted in any medium without royalty provided the copyright
  6 + notice and this notice are preserved. -->
  7 +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
  8 +<feature name="org.gnu.gdb.arm.vfp">
  9 + <reg name="d0" bitsize="64" type="float"/>
  10 + <reg name="d1" bitsize="64" type="float"/>
  11 + <reg name="d2" bitsize="64" type="float"/>
  12 + <reg name="d3" bitsize="64" type="float"/>
  13 + <reg name="d4" bitsize="64" type="float"/>
  14 + <reg name="d5" bitsize="64" type="float"/>
  15 + <reg name="d6" bitsize="64" type="float"/>
  16 + <reg name="d7" bitsize="64" type="float"/>
  17 + <reg name="d8" bitsize="64" type="float"/>
  18 + <reg name="d9" bitsize="64" type="float"/>
  19 + <reg name="d10" bitsize="64" type="float"/>
  20 + <reg name="d11" bitsize="64" type="float"/>
  21 + <reg name="d12" bitsize="64" type="float"/>
  22 + <reg name="d13" bitsize="64" type="float"/>
  23 + <reg name="d14" bitsize="64" type="float"/>
  24 + <reg name="d15" bitsize="64" type="float"/>
  25 +
  26 + <reg name="fpsid" bitsize="32" type="int" group="float"/>
  27 + <reg name="fpscr" bitsize="32" type="int" group="float"/>
  28 + <reg name="fpexc" bitsize="32" type="int" group="float"/>
  29 +</feature>
... ...
gdb-xml/arm-vfp3.xml 0 → 100644
  View file @56aebc8
  1 +<?xml version="1.0"?>
  2 +<!-- Copyright (C) 2008 Free Software Foundation, Inc.
  3 +
  4 + Copying and distribution of this file, with or without modification,
  5 + are permitted in any medium without royalty provided the copyright
  6 + notice and this notice are preserved. -->
  7 +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
  8 +<feature name="org.gnu.gdb.arm.vfpv3">
  9 + <reg name="d0" bitsize="64" type="float"/>
  10 + <reg name="d1" bitsize="64" type="float"/>
  11 + <reg name="d2" bitsize="64" type="float"/>
  12 + <reg name="d3" bitsize="64" type="float"/>
  13 + <reg name="d4" bitsize="64" type="float"/>
  14 + <reg name="d5" bitsize="64" type="float"/>
  15 + <reg name="d6" bitsize="64" type="float"/>
  16 + <reg name="d7" bitsize="64" type="float"/>
  17 + <reg name="d8" bitsize="64" type="float"/>
  18 + <reg name="d9" bitsize="64" type="float"/>
  19 + <reg name="d10" bitsize="64" type="float"/>
  20 + <reg name="d11" bitsize="64" type="float"/>
  21 + <reg name="d12" bitsize="64" type="float"/>
  22 + <reg name="d13" bitsize="64" type="float"/>
  23 + <reg name="d14" bitsize="64" type="float"/>
  24 + <reg name="d15" bitsize="64" type="float"/>
  25 + <reg name="d16" bitsize="64" type="float"/>
  26 + <reg name="d17" bitsize="64" type="float"/>
  27 + <reg name="d18" bitsize="64" type="float"/>
  28 + <reg name="d19" bitsize="64" type="float"/>
  29 + <reg name="d20" bitsize="64" type="float"/>
  30 + <reg name="d21" bitsize="64" type="float"/>
  31 + <reg name="d22" bitsize="64" type="float"/>
  32 + <reg name="d23" bitsize="64" type="float"/>
  33 + <reg name="d24" bitsize="64" type="float"/>
  34 + <reg name="d25" bitsize="64" type="float"/>
  35 + <reg name="d26" bitsize="64" type="float"/>
  36 + <reg name="d27" bitsize="64" type="float"/>
  37 + <reg name="d28" bitsize="64" type="float"/>
  38 + <reg name="d29" bitsize="64" type="float"/>
  39 + <reg name="d30" bitsize="64" type="float"/>
  40 + <reg name="d31" bitsize="64" type="float"/>
  41 +
  42 + <reg name="fpsid" bitsize="32" type="int" group="float"/>
  43 + <reg name="fpscr" bitsize="32" type="int" group="float"/>
  44 + <reg name="fpexc" bitsize="32" type="int" group="float"/>
  45 +</feature>
... ...
gdb-xml/cf-core.xml 0 → 100644
  View file @56aebc8
  1 +<?xml version="1.0"?>
  2 +<!-- Copyright (C) 2008 Free Software Foundation, Inc.
  3 +
  4 + Copying and distribution of this file, with or without modification,
  5 + are permitted in any medium without royalty provided the copyright
  6 + notice and this notice are preserved. -->
  7 +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
  8 +<feature name="org.gnu.gdb.coldfire.core">
  9 + <reg name="d0" bitsize="32"/>
  10 + <reg name="d1" bitsize="32"/>
  11 + <reg name="d2" bitsize="32"/>
  12 + <reg name="d3" bitsize="32"/>
  13 + <reg name="d4" bitsize="32"/>
  14 + <reg name="d5" bitsize="32"/>
  15 + <reg name="d6" bitsize="32"/>
  16 + <reg name="d7" bitsize="32"/>
  17 + <reg name="a0" bitsize="32" type="data_ptr"/>
  18 + <reg name="a1" bitsize="32" type="data_ptr"/>
  19 + <reg name="a2" bitsize="32" type="data_ptr"/>
  20 + <reg name="a3" bitsize="32" type="data_ptr"/>
  21 + <reg name="a4" bitsize="32" type="data_ptr"/>
  22 + <reg name="a5" bitsize="32" type="data_ptr"/>
  23 + <reg name="fp" bitsize="32" type="data_ptr"/>
  24 + <reg name="sp" bitsize="32" type="data_ptr"/>
  25 +
  26 + <reg name="ps" bitsize="32"/>
  27 + <reg name="pc" bitsize="32" type="code_ptr"/>
  28 +
  29 +</feature>
... ...
gdb-xml/cf-fp.xml 0 → 100644
  View file @56aebc8
  1 +<?xml version="1.0"?>
  2 +<!-- Copyright (C) 2008 Free Software Foundation, Inc.
  3 +
  4 + Copying and distribution of this file, with or without modification,
  5 + are permitted in any medium without royalty provided the copyright
  6 + notice and this notice are preserved. -->
  7 +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
  8 +<feature name="org.gnu.gdb.coldfire.fp">
  9 + <reg name="fp0" bitsize="64" type="float" group="float"/>
  10 + <reg name="fp1" bitsize="64" type="float" group="float"/>
  11 + <reg name="fp2" bitsize="64" type="float" group="float"/>
  12 + <reg name="fp3" bitsize="64" type="float" group="float"/>
  13 + <reg name="fp4" bitsize="64" type="float" group="float"/>
  14 + <reg name="fp5" bitsize="64" type="float" group="float"/>
  15 + <reg name="fp6" bitsize="64" type="float" group="float"/>
  16 + <reg name="fp7" bitsize="64" type="float" group="float"/>
  17 +
  18 +
  19 + <reg name="fpcontrol" bitsize="32" group="float"/>
  20 + <reg name="fpstatus" bitsize="32" group="float"/>,
  21 + <reg name="fpiaddr" bitsize="32" type="code_ptr" group="float"/>
  22 +</feature>
... ...
gdbstub.c
  View file @56aebc8
... ... @@ -18,6 +18,7 @@
18 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 */
20 20 #include "config.h"
  21 +#include "qemu-common.h"
21 22 #ifdef CONFIG_USER_ONLY
22 23 #include <stdlib.h>
23 24 #include <stdio.h>
... ... @@ -29,12 +30,13 @@
29 30  
30 31 #include "qemu.h"
31 32 #else
32   -#include "qemu-common.h"
33 33 #include "qemu-char.h"
34 34 #include "sysemu.h"
35 35 #include "gdbstub.h"
36 36 #endif
37 37  
  38 +#define MAX_PACKET_LENGTH 4096
  39 +
38 40 #include "qemu_socket.h"
39 41 #ifdef _WIN32
40 42 /* XXX: these constants may be independent of the host ones even for Unix */
... ... @@ -50,6 +52,15 @@
50 52  
51 53 //#define DEBUG_GDB
52 54  
  55 +typedef struct GDBRegisterState {
  56 + int base_reg;
  57 + int num_regs;
  58 + gdb_reg_cb get_reg;
  59 + gdb_reg_cb set_reg;
  60 + const char *xml;
  61 + struct GDBRegisterState *next;
  62 +} GDBRegisterState;
  63 +
53 64 enum RSState {
54 65 RS_IDLE,
55 66 RS_GETLINE,
... ... @@ -60,10 +71,10 @@ enum RSState {
60 71 typedef struct GDBState {
61 72 CPUState *env; /* current CPU */
62 73 enum RSState state; /* parsing state */
63   - char line_buf[4096];
  74 + char line_buf[MAX_PACKET_LENGTH];
64 75 int line_buf_index;
65 76 int line_csum;
66   - uint8_t last_packet[4100];
  77 + uint8_t last_packet[MAX_PACKET_LENGTH + 4];
67 78 int last_packet_len;
68 79 int signal;
69 80 #ifdef CONFIG_USER_ONLY
... ... @@ -79,6 +90,11 @@ typedef struct GDBState {
79 90 */
80 91 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
81 92  
  93 +/* This is an ugly hack to cope with both new and old gdb.
  94 + If gdb sends qXfer:features:read then assume we're talking to a newish
  95 + gdb that understands target descriptions. */
  96 +static int gdb_has_xml;
  97 +
82 98 #ifdef CONFIG_USER_ONLY
83 99 /* XXX: This is not thread safe. Do we care? */
84 100 static int gdbserver_fd = -1;
... ... @@ -205,19 +221,14 @@ static void hextomem(uint8_t *mem, const char *buf, int len)
205 221 }
206 222  
207 223 /* return -1 if error, 0 if OK */
208   -static int put_packet(GDBState *s, const char *buf)
  224 +static int put_packet_binary(GDBState *s, const char *buf, int len)
209 225 {
210   - int len, csum, i;
  226 + int csum, i;
211 227 uint8_t *p;
212 228  
213   -#ifdef DEBUG_GDB
214   - printf("reply='%s'\n", buf);
215   -#endif
216   -
217 229 for(;;) {
218 230 p = s->last_packet;
219 231 *(p++) = '$';
220   - len = strlen(buf);
221 232 memcpy(p, buf, len);
222 233 p += len;
223 234 csum = 0;
... ... @@ -244,522 +255,539 @@ static int put_packet(GDBState *s, const char *buf)
244 255 return 0;
245 256 }
246 257  
247   -#if defined(TARGET_I386)
  258 +/* return -1 if error, 0 if OK */
  259 +static int put_packet(GDBState *s, const char *buf)
  260 +{
  261 +#ifdef DEBUG_GDB
  262 + printf("reply='%s'\n", buf);
  263 +#endif
248 264  
249   -#ifdef TARGET_X86_64
250   -static const uint8_t gdb_x86_64_regs[16] = {
251   - R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
252   - 8, 9, 10, 11, 12, 13, 14, 15,
253   -};
  265 + return put_packet_binary(s, buf, strlen(buf));
  266 +}
  267 +
  268 +/* The GDB remote protocol transfers values in target byte order. This means
  269 + we can use the raw memory access routines to access the value buffer.
  270 + Conveniently, these also handle the case where the buffer is mis-aligned.
  271 + */
  272 +#define GET_REG8(val) do { \
  273 + stb_p(mem_buf, val); \
  274 + return 1; \
  275 + } while(0)
  276 +#define GET_REG16(val) do { \
  277 + stw_p(mem_buf, val); \
  278 + return 2; \
  279 + } while(0)
  280 +#define GET_REG32(val) do { \
  281 + stl_p(mem_buf, val); \
  282 + return 4; \
  283 + } while(0)
  284 +#define GET_REG64(val) do { \
  285 + stq_p(mem_buf, val); \
  286 + return 8; \
  287 + } while(0)
  288 +
  289 +#if TARGET_LONG_BITS == 64
  290 +#define GET_REGL(val) GET_REG64(val)
  291 +#define ldtul_p(addr) ldq_p(addr)
  292 +#else
  293 +#define GET_REGL(val) GET_REG32(val)
  294 +#define ldtul_p(addr) ldl_p(addr)
254 295 #endif
255 296  
256   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
257   -{
258   - int i, fpus, nb_regs;
259   - uint8_t *p;
  297 +#if defined(TARGET_I386)
260 298  
261   - p = mem_buf;
262 299 #ifdef TARGET_X86_64
263   - if (env->hflags & HF_CS64_MASK) {
264   - nb_regs = 16;
265   - for(i = 0; i < 16; i++) {
266   - *(uint64_t *)p = tswap64(env->regs[gdb_x86_64_regs[i]]);
267   - p += 8;
268   - }
269   - *(uint64_t *)p = tswap64(env->eip);
270   - p += 8;
271   - } else
272   -#endif
273   - {
274   - nb_regs = 8;
275   - for(i = 0; i < 8; i++) {
276   - *(uint32_t *)p = tswap32(env->regs[i]);
277   - p += 4;
278   - }
279   - *(uint32_t *)p = tswap32(env->eip);
280   - p += 4;
281   - }
282   -
283   - *(uint32_t *)p = tswap32(env->eflags);
284   - p += 4;
285   - *(uint32_t *)p = tswap32(env->segs[R_CS].selector);
286   - p += 4;
287   - *(uint32_t *)p = tswap32(env->segs[R_SS].selector);
288   - p += 4;
289   - *(uint32_t *)p = tswap32(env->segs[R_DS].selector);
290   - p += 4;
291   - *(uint32_t *)p = tswap32(env->segs[R_ES].selector);
292   - p += 4;
293   - *(uint32_t *)p = tswap32(env->segs[R_FS].selector);
294   - p += 4;
295   - *(uint32_t *)p = tswap32(env->segs[R_GS].selector);
296   - p += 4;
297   - for(i = 0; i < 8; i++) {
298   - /* XXX: convert floats */
299   -#ifdef USE_X86LDOUBLE
300   - memcpy(p, &env->fpregs[i], 10);
  300 +static const int gpr_map[16] = {
  301 + R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
  302 + 8, 9, 10, 11, 12, 13, 14, 15
  303 +};
301 304 #else
302   - memset(p, 0, 10);
  305 +static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
303 306 #endif
304   - p += 10;
305   - }
306   - *(uint32_t *)p = tswap32(env->fpuc); /* fctrl */
307   - p += 4;
308   - fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
309   - *(uint32_t *)p = tswap32(fpus); /* fstat */
310   - p += 4;
311   - *(uint32_t *)p = 0; /* ftag */
312   - p += 4;
313   - *(uint32_t *)p = 0; /* fiseg */
314   - p += 4;
315   - *(uint32_t *)p = 0; /* fioff */
316   - p += 4;
317   - *(uint32_t *)p = 0; /* foseg */
318   - p += 4;
319   - *(uint32_t *)p = 0; /* fooff */
320   - p += 4;
321   - *(uint32_t *)p = 0; /* fop */
322   - p += 4;
323   - for(i = 0; i < nb_regs; i++) {
324   - *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(0));
325   - p += 8;
326   - *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(1));
327   - p += 8;
328   - }
329   - *(uint32_t *)p = tswap32(env->mxcsr);
330   - p += 4;
331   - return p - mem_buf;
332   -}
333 307  
334   -static inline void cpu_gdb_load_seg(CPUState *env, const uint8_t **pp,
335   - int sreg)
  308 +#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
  309 +
  310 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
336 311 {
337   - const uint8_t *p;
338   - uint32_t sel;
339   - p = *pp;
340   - sel = tswap32(*(uint32_t *)p);
341   - p += 4;
342   - if (sel != env->segs[sreg].selector) {
343   -#if defined(CONFIG_USER_ONLY)
344   - cpu_x86_load_seg(env, sreg, sel);
  312 + if (n < CPU_NB_REGS) {
  313 + GET_REGL(env->regs[gpr_map[n]]);
  314 + } else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) {
  315 + /* FIXME: byteswap float values. */
  316 +#ifdef USE_X86LDOUBLE
  317 + memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10);
345 318 #else
346   - /* XXX: do it with a debug function which does not raise an
347   - exception */
  319 + memset(mem_buf, 0, 10);
348 320 #endif
  321 + return 10;
  322 + } else if (n >= CPU_NB_REGS + 24) {
  323 + n -= CPU_NB_REGS + 24;
  324 + if (n < CPU_NB_REGS) {
  325 + stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
  326 + stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
  327 + return 16;
  328 + } else if (n == CPU_NB_REGS) {
  329 + GET_REG32(env->mxcsr);
  330 + }
  331 + } else {
  332 + n -= CPU_NB_REGS;
  333 + switch (n) {
  334 + case 0: GET_REGL(env->eip);
  335 + case 1: GET_REG32(env->eflags);
  336 + case 2: GET_REG32(env->segs[R_CS].selector);
  337 + case 3: GET_REG32(env->segs[R_SS].selector);
  338 + case 4: GET_REG32(env->segs[R_DS].selector);
  339 + case 5: GET_REG32(env->segs[R_ES].selector);
  340 + case 6: GET_REG32(env->segs[R_FS].selector);
  341 + case 7: GET_REG32(env->segs[R_GS].selector);
  342 + /* 8...15 x87 regs. */
  343 + case 16: GET_REG32(env->fpuc);
  344 + case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11);
  345 + case 18: GET_REG32(0); /* ftag */
  346 + case 19: GET_REG32(0); /* fiseg */
  347 + case 20: GET_REG32(0); /* fioff */
  348 + case 21: GET_REG32(0); /* foseg */
  349 + case 22: GET_REG32(0); /* fooff */
  350 + case 23: GET_REG32(0); /* fop */
  351 + /* 24+ xmm regs. */
  352 + }
349 353 }
350   - *pp = p;
  354 + return 0;
351 355 }
352 356  
353   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  357 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)
354 358 {
355   - const uint8_t *p = mem_buf;
356   - int i, nb_regs;
357   - uint16_t fpus;
  359 + uint32_t tmp;
358 360  
359   -#ifdef TARGET_X86_64
360   - if (env->hflags & HF_CS64_MASK) {
361   - nb_regs = 16;
362   - for(i = 0; i < 16; i++) {
363   - env->regs[gdb_x86_64_regs[i]] = tswap64(*(uint64_t *)p);
364   - p += 8;
365   - }
366   - env->eip = tswap64(*(uint64_t *)p);
367   - p += 8;
368   - } else
  361 + if (i < CPU_NB_REGS) {
  362 + env->regs[gpr_map[i]] = ldtul_p(mem_buf);
  363 + return sizeof(target_ulong);
  364 + } else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) {
  365 + i -= CPU_NB_REGS + 8;
  366 +#ifdef USE_X86LDOUBLE
  367 + memcpy(&env->fpregs[i], mem_buf, 10);
369 368 #endif
370   - {
371   - nb_regs = 8;
372   - for(i = 0; i < 8; i++) {
373   - env->regs[i] = tswap32(*(uint32_t *)p);
374   - p += 4;
  369 + return 10;
  370 + } else if (i >= CPU_NB_REGS + 24) {
  371 + i -= CPU_NB_REGS + 24;
  372 + if (i < CPU_NB_REGS) {
  373 + env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf);
  374 + env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8);
  375 + return 16;
  376 + } else if (i == CPU_NB_REGS) {
  377 + env->mxcsr = ldl_p(mem_buf);
  378 + return 4;
375 379 }
376   - env->eip = tswap32(*(uint32_t *)p);
377   - p += 4;
378   - }
379   - env->eflags = tswap32(*(uint32_t *)p);
380   - p += 4;
381   - cpu_gdb_load_seg(env, &p, R_CS);
382   - cpu_gdb_load_seg(env, &p, R_SS);
383   - cpu_gdb_load_seg(env, &p, R_DS);
384   - cpu_gdb_load_seg(env, &p, R_ES);
385   - cpu_gdb_load_seg(env, &p, R_FS);
386   - cpu_gdb_load_seg(env, &p, R_GS);
387   -
388   - /* FPU state */
389   - for(i = 0; i < 8; i++) {
390   - /* XXX: convert floats */
391   -#ifdef USE_X86LDOUBLE
392   - memcpy(&env->fpregs[i], p, 10);
  380 + } else {
  381 + i -= CPU_NB_REGS;
  382 + switch (i) {
  383 + case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong);
  384 + case 1: env->eflags = ldl_p(mem_buf); return 4;
  385 +#if defined(CONFIG_USER_ONLY)
  386 +#define LOAD_SEG(index, sreg)\
  387 + tmp = ldl_p(mem_buf);\
  388 + if (tmp != env->segs[sreg].selector)\
  389 + cpu_x86_load_seg(env, sreg, tmp);
  390 +#else
  391 +/* FIXME: Honor segment registers. Needs to avoid raising an exception
  392 + when the selector is invalid. */
  393 +#define LOAD_SEG(index, sreg) do {} while(0)
393 394 #endif
394   - p += 10;
395   - }
396   - env->fpuc = tswap32(*(uint32_t *)p); /* fctrl */
397   - p += 4;
398   - fpus = tswap32(*(uint32_t *)p);
399   - p += 4;
400   - env->fpstt = (fpus >> 11) & 7;
401   - env->fpus = fpus & ~0x3800;
402   - p += 4 * 6;
403   -
404   - if (size >= ((p - mem_buf) + 16 * nb_regs + 4)) {
405   - /* SSE state */
406   - for(i = 0; i < nb_regs; i++) {
407   - env->xmm_regs[i].XMM_Q(0) = tswap64(*(uint64_t *)p);
408   - p += 8;
409   - env->xmm_regs[i].XMM_Q(1) = tswap64(*(uint64_t *)p);
410   - p += 8;
  395 + case 2: LOAD_SEG(10, R_CS); return 4;
  396 + case 3: LOAD_SEG(11, R_SS); return 4;
  397 + case 4: LOAD_SEG(12, R_DS); return 4;
  398 + case 5: LOAD_SEG(13, R_ES); return 4;
  399 + case 6: LOAD_SEG(14, R_FS); return 4;
  400 + case 7: LOAD_SEG(15, R_GS); return 4;
  401 + /* 8...15 x87 regs. */
  402 + case 16: env->fpuc = ldl_p(mem_buf); return 4;
  403 + case 17:
  404 + tmp = ldl_p(mem_buf);
  405 + env->fpstt = (tmp >> 11) & 7;
  406 + env->fpus = tmp & ~0x3800;
  407 + return 4;
  408 + case 18: /* ftag */ return 4;
  409 + case 19: /* fiseg */ return 4;
  410 + case 20: /* fioff */ return 4;
  411 + case 21: /* foseg */ return 4;
  412 + case 22: /* fooff */ return 4;
  413 + case 23: /* fop */ return 4;
  414 + /* 24+ xmm regs. */
411 415 }
412   - env->mxcsr = tswap32(*(uint32_t *)p);
413   - p += 4;
414 416 }
  417 + /* Unrecognised register. */
  418 + return 0;
415 419 }
416 420  
417 421 #elif defined (TARGET_PPC)
418   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
419   -{
420   - uint32_t *registers = (uint32_t *)mem_buf, tmp;
421   - int i;
422 422  
423   - /* fill in gprs */
424   - for(i = 0; i < 32; i++) {
425   - registers[i] = tswapl(env->gpr[i]);
426   - }
427   - /* fill in fprs */
428   - for (i = 0; i < 32; i++) {
429   - registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
430   - registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
431   - }
432   - /* nip, msr, ccr, lnk, ctr, xer, mq */
433   - registers[96] = tswapl(env->nip);
434   - registers[97] = tswapl(env->msr);
435   - tmp = 0;
436   - for (i = 0; i < 8; i++)
437   - tmp |= env->crf[i] << (32 - ((i + 1) * 4));
438   - registers[98] = tswapl(tmp);
439   - registers[99] = tswapl(env->lr);
440   - registers[100] = tswapl(env->ctr);
441   - registers[101] = tswapl(ppc_load_xer(env));
442   - registers[102] = 0;
443   -
444   - return 103 * 4;
445   -}
  423 +#define NUM_CORE_REGS 71
446 424  
447   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  425 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
448 426 {
449   - uint32_t *registers = (uint32_t *)mem_buf;
450   - int i;
  427 + if (n < 32) {
  428 + /* gprs */
  429 + GET_REGL(env->gpr[n]);
  430 + } else if (n < 64) {
  431 + /* fprs */
  432 + stfq_p(mem_buf, env->fpr[n]);
  433 + return 8;
  434 + } else {
  435 + switch (n) {
  436 + case 64: GET_REGL(env->nip);
  437 + case 65: GET_REGL(env->msr);
  438 + case 66:
  439 + {
  440 + uint32_t cr = 0;
  441 + int i;
  442 + for (i = 0; i < 8; i++)
  443 + cr |= env->crf[i] << (32 - ((i + 1) * 4));
  444 + GET_REG32(cr);
  445 + }
  446 + case 67: GET_REGL(env->lr);
  447 + case 68: GET_REGL(env->ctr);
  448 + case 69: GET_REG32(ppc_load_xer(env));
  449 + case 70: GET_REG32(0); /* fpscr */
  450 + }
  451 + }
  452 + return 0;
  453 +}
451 454  
452   - /* fill in gprs */
453   - for (i = 0; i < 32; i++) {
454   - env->gpr[i] = tswapl(registers[i]);
455   - }
456   - /* fill in fprs */
457   - for (i = 0; i < 32; i++) {
458   - *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
459   - *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
460   - }
461   - /* nip, msr, ccr, lnk, ctr, xer, mq */
462   - env->nip = tswapl(registers[96]);
463   - ppc_store_msr(env, tswapl(registers[97]));
464   - registers[98] = tswapl(registers[98]);
465   - for (i = 0; i < 8; i++)
466   - env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
467   - env->lr = tswapl(registers[99]);
468   - env->ctr = tswapl(registers[100]);
469   - ppc_store_xer(env, tswapl(registers[101]));
  455 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
  456 +{
  457 + if (n < 32) {
  458 + /* gprs */
  459 + env->gpr[n] = ldtul_p(mem_buf);
  460 + return sizeof(target_ulong);
  461 + } else if (n < 64) {
  462 + /* fprs */
  463 + env->fpr[n] = ldfq_p(mem_buf);
  464 + return 8;
  465 + } else {
  466 + switch (n) {
  467 + case 64:
  468 + env->nip = ldtul_p(mem_buf);
  469 + return sizeof(target_ulong);
  470 + case 65:
  471 + ppc_store_msr(env, ldtul_p(mem_buf));
  472 + return sizeof(target_ulong);
  473 + case 66:
  474 + {
  475 + uint32_t cr = ldl_p(mem_buf);
  476 + int i;
  477 + for (i = 0; i < 8; i++)
  478 + env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
  479 + return 4;
  480 + }
  481 + case 67:
  482 + env->lr = ldtul_p(mem_buf);
  483 + return sizeof(target_ulong);
  484 + case 68:
  485 + env->ctr = ldtul_p(mem_buf);
  486 + return sizeof(target_ulong);
  487 + case 69:
  488 + ppc_store_xer(env, ldl_p(mem_buf));
  489 + return 4;
  490 + case 70:
  491 + /* fpscr */
  492 + return 4;
  493 + }
  494 + }
  495 + return 0;
470 496 }
  497 +
471 498 #elif defined (TARGET_SPARC)
472   -#ifdef TARGET_ABI32
473   -#define tswap_abi(val) tswap32(val &0xffffffff)
  499 +
  500 +#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
  501 +#define NUM_CORE_REGS 86
474 502 #else
475   -#define tswap_abi(val) tswapl(val)
  503 +#define NUM_CORE_REGS 73
476 504 #endif
477   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
478   -{
  505 +
479 506 #ifdef TARGET_ABI32
480   - abi_ulong *registers = (abi_ulong *)mem_buf;
  507 +#define GET_REGA(val) GET_REG32(val)
481 508 #else
482   - target_ulong *registers = (target_ulong *)mem_buf;
  509 +#define GET_REGA(val) GET_REGL(val)
483 510 #endif
484   - int i;
485 511  
486   - /* fill in g0..g7 */
487   - for(i = 0; i < 8; i++) {
488   - registers[i] = tswap_abi(env->gregs[i]);
  512 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
  513 +{
  514 + if (n < 8) {
  515 + /* g0..g7 */
  516 + GET_REGA(env->gregs[n]);
489 517 }
490   - /* fill in register window */
491   - for(i = 0; i < 24; i++) {
492   - registers[i + 8] = tswap_abi(env->regwptr[i]);
  518 + if (n < 32) {
  519 + /* register window */
  520 + GET_REGA(env->regwptr[n - 8]);
493 521 }
494   -#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
495   - /* fill in fprs */
496   - for (i = 0; i < 32; i++) {
497   - registers[i + 32] = tswap_abi(*((uint32_t *)&env->fpr[i]));
  522 +#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
  523 + if (n < 64) {
  524 + /* fprs */
  525 + GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
498 526 }
499 527 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
500   - registers[64] = tswap_abi(env->y);
501   - {
502   - uint32_t tmp;
503   -
504   - tmp = GET_PSR(env);
505   - registers[65] = tswap32(tmp);
506   - }
507   - registers[66] = tswap_abi(env->wim);
508   - registers[67] = tswap_abi(env->tbr);
509   - registers[68] = tswap_abi(env->pc);
510   - registers[69] = tswap_abi(env->npc);
511   - registers[70] = tswap_abi(env->fsr);
512   - registers[71] = 0; /* csr */
513   - registers[72] = 0;
514   - return 73 * sizeof(uint32_t);
  528 + switch (n) {
  529 + case 64: GET_REGA(env->y);
  530 + case 65: GET_REGA(GET_PSR(env));
  531 + case 66: GET_REGA(env->wim);
  532 + case 67: GET_REGA(env->tbr);
  533 + case 68: GET_REGA(env->pc);
  534 + case 69: GET_REGA(env->npc);
  535 + case 70: GET_REGA(env->fsr);
  536 + case 71: GET_REGA(0); /* csr */
  537 + case 72: GET_REGA(0);
  538 + }
515 539 #else
516   - /* fill in fprs */
517   - for (i = 0; i < 64; i += 2) {
518   - uint64_t tmp;
  540 + if (n < 64) {
  541 + /* f0-f31 */
  542 + GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
  543 + }
  544 + if (n < 80) {
  545 + /* f32-f62 (double width, even numbers only) */
  546 + uint64_t val;
519 547  
520   - tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
521   - tmp |= *(uint32_t *)&env->fpr[i + 1];
522   - registers[i / 2 + 32] = tswap64(tmp);
  548 + val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
  549 + val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
  550 + GET_REG64(val);
523 551 }
524   - registers[64] = tswapl(env->pc);
525   - registers[65] = tswapl(env->npc);
526   - registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
  552 + switch (n) {
  553 + case 80: GET_REGL(env->pc);
  554 + case 81: GET_REGL(env->npc);
  555 + case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
527 556 ((env->asi & 0xff) << 24) |
528 557 ((env->pstate & 0xfff) << 8) |
529 558 GET_CWP64(env));
530   - registers[67] = tswapl(env->fsr);
531   - registers[68] = tswapl(env->fprs);
532   - registers[69] = tswapl(env->y);
533   - return 70 * sizeof(target_ulong);
  559 + case 83: GET_REGL(env->fsr);
  560 + case 84: GET_REGL(env->fprs);
  561 + case 85: GET_REGL(env->y);
  562 + }
534 563 #endif
  564 + return 0;
535 565 }
536 566  
537   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  567 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
538 568 {
539   -#ifdef TARGET_ABI32
540   - abi_ulong *registers = (abi_ulong *)mem_buf;
  569 +#if defined(TARGET_ABI32)
  570 + abi_ulong tmp;
  571 +
  572 + tmp = ldl_p(mem_buf);
541 573 #else
542   - target_ulong *registers = (target_ulong *)mem_buf;
  574 + target_ulong tmp;
  575 +
  576 + tmp = ldtul_p(mem_buf);
543 577 #endif
544   - int i;
545 578  
546   - /* fill in g0..g7 */
547   - for(i = 0; i < 7; i++) {
548   - env->gregs[i] = tswap_abi(registers[i]);
  579 + if (n < 8) {
  580 + /* g0..g7 */
  581 + env->gregs[n] = tmp;
  582 + } else if (n < 32) {
  583 + /* register window */
  584 + env->regwptr[n - 8] = tmp;
549 585 }
550   - /* fill in register window */
551   - for(i = 0; i < 24; i++) {
552   - env->regwptr[i] = tswap_abi(registers[i + 8]);
553   - }
554   -#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
555   - /* fill in fprs */
556   - for (i = 0; i < 32; i++) {
557   - *((uint32_t *)&env->fpr[i]) = tswap_abi(registers[i + 32]);
  586 +#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
  587 + else if (n < 64) {
  588 + /* fprs */
  589 + *((uint32_t *)&env->fpr[n - 32]) = tmp;
  590 + } else {
  591 + /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
  592 + switch (n) {
  593 + case 64: env->y = tmp; break;
  594 + case 65: PUT_PSR(env, tmp); break;
  595 + case 66: env->wim = tmp; break;
  596 + case 67: env->tbr = tmp; break;
  597 + case 68: env->pc = tmp; break;
  598 + case 69: env->npc = tmp; break;
  599 + case 70: env->fsr = tmp; break;
  600 + default: return 0;
  601 + }
558 602 }
559   - /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
560   - env->y = tswap_abi(registers[64]);
561   - PUT_PSR(env, tswap_abi(registers[65]));
562   - env->wim = tswap_abi(registers[66]);
563   - env->tbr = tswap_abi(registers[67]);
564   - env->pc = tswap_abi(registers[68]);
565   - env->npc = tswap_abi(registers[69]);
566   - env->fsr = tswap_abi(registers[70]);
  603 + return 4;
567 604 #else
568   - for (i = 0; i < 64; i += 2) {
569   - uint64_t tmp;
570   -
571   - tmp = tswap64(registers[i / 2 + 32]);
572   - *((uint32_t *)&env->fpr[i]) = tmp >> 32;
573   - *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
574   - }
575   - env->pc = tswapl(registers[64]);
576   - env->npc = tswapl(registers[65]);
577   - {
578   - uint64_t tmp = tswapl(registers[66]);
579   -
580   - PUT_CCR(env, tmp >> 32);
581   - env->asi = (tmp >> 24) & 0xff;
582   - env->pstate = (tmp >> 8) & 0xfff;
583   - PUT_CWP64(env, tmp & 0xff);
  605 + else if (n < 64) {
  606 + /* f0-f31 */
  607 + uint32_t fpr;
  608 +
  609 + env->fpr[n] = ldfl_p(mem_buf);
  610 + return 4;
  611 + } else if (n < 80) {
  612 + /* f32-f62 (double width, even numbers only) */
  613 + *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
  614 + *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
  615 + } else {
  616 + switch (n) {
  617 + case 80: env->pc = tmp; break;
  618 + case 81: env->npc = tmp; break;
  619 + case 82:
  620 + PUT_CCR(env, tmp >> 32);
  621 + env->asi = (tmp >> 24) & 0xff;
  622 + env->pstate = (tmp >> 8) & 0xfff;
  623 + PUT_CWP64(env, tmp & 0xff);
  624 + break;
  625 + case 83: env->fsr = tmp; break;
  626 + case 84: env->fprs = tmp; break;
  627 + case 85: env->y = tmp; break;
  628 + default: return 0;
  629 + }
584 630 }
585   - env->fsr = tswapl(registers[67]);
586   - env->fprs = tswapl(registers[68]);
587   - env->y = tswapl(registers[69]);
  631 + return 8;
588 632 #endif
589 633 }
590   -#undef tswap_abi
591 634 #elif defined (TARGET_ARM)
592   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
593   -{
594   - int i;
595   - uint8_t *ptr;
596   -
597   - ptr = mem_buf;
598   - /* 16 core integer registers (4 bytes each). */
599   - for (i = 0; i < 16; i++)
600   - {
601   - *(uint32_t *)ptr = tswapl(env->regs[i]);
602   - ptr += 4;
603   - }
604   - /* 8 FPA registers (12 bytes each), FPS (4 bytes).
605   - Not yet implemented. */
606   - memset (ptr, 0, 8 * 12 + 4);
607   - ptr += 8 * 12 + 4;
608   - /* CPSR (4 bytes). */
609   - *(uint32_t *)ptr = tswapl (cpsr_read(env));
610   - ptr += 4;
611   -
612   - return ptr - mem_buf;
613   -}
614 635  
615   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
616   -{
617   - int i;
618   - uint8_t *ptr;
619   -
620   - ptr = mem_buf;
621   - /* Core integer registers. */
622   - for (i = 0; i < 16; i++)
623   - {
624   - env->regs[i] = tswapl(*(uint32_t *)ptr);
625   - ptr += 4;
626   - }
627   - /* Ignore FPA regs and scr. */
628   - ptr += 8 * 12 + 4;
629   - cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
630   -}
631   -#elif defined (TARGET_M68K)
632   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
633   -{
634   - int i;
635   - uint8_t *ptr;
636   - CPU_DoubleU u;
637   -
638   - ptr = mem_buf;
639   - /* D0-D7 */
640   - for (i = 0; i < 8; i++) {
641   - *(uint32_t *)ptr = tswapl(env->dregs[i]);
642   - ptr += 4;
643   - }
644   - /* A0-A7 */
645   - for (i = 0; i < 8; i++) {
646   - *(uint32_t *)ptr = tswapl(env->aregs[i]);
647   - ptr += 4;
648   - }
649   - *(uint32_t *)ptr = tswapl(env->sr);
650   - ptr += 4;
651   - *(uint32_t *)ptr = tswapl(env->pc);
652   - ptr += 4;
653   - /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
654   - ColdFire has 8-bit double precision registers. */
655   - for (i = 0; i < 8; i++) {
656   - u.d = env->fregs[i];
657   - *(uint32_t *)ptr = tswap32(u.l.upper);
658   - *(uint32_t *)ptr = tswap32(u.l.lower);
659   - }
660   - /* FP control regs (not implemented). */
661   - memset (ptr, 0, 3 * 4);
662   - ptr += 3 * 4;
663   -
664   - return ptr - mem_buf;
665   -}
  636 +/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
  637 + whatever the target description contains. Due to a historical mishap
  638 + the FPA registers appear in between core integer regs and the CPSR.
  639 + We hack round this by giving the FPA regs zero size when talking to a
  640 + newer gdb. */
  641 +#define NUM_CORE_REGS 26
  642 +#define GDB_CORE_XML "arm-core.xml"
666 643  
667   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  644 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
668 645 {
669   - int i;
670   - uint8_t *ptr;
671   - CPU_DoubleU u;
672   -
673   - ptr = mem_buf;
674   - /* D0-D7 */
675   - for (i = 0; i < 8; i++) {
676   - env->dregs[i] = tswapl(*(uint32_t *)ptr);
677   - ptr += 4;
678   - }
679   - /* A0-A7 */
680   - for (i = 0; i < 8; i++) {
681   - env->aregs[i] = tswapl(*(uint32_t *)ptr);
682   - ptr += 4;
683   - }
684   - env->sr = tswapl(*(uint32_t *)ptr);
685   - ptr += 4;
686   - env->pc = tswapl(*(uint32_t *)ptr);
687   - ptr += 4;
688   - /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
689   - ColdFire has 8-bit double precision registers. */
690   - for (i = 0; i < 8; i++) {
691   - u.l.upper = tswap32(*(uint32_t *)ptr);
692   - u.l.lower = tswap32(*(uint32_t *)ptr);
693   - env->fregs[i] = u.d;
694   - }
695   - /* FP control regs (not implemented). */
696   - ptr += 3 * 4;
  646 + if (n < 16) {
  647 + /* Core integer register. */
  648 + GET_REG32(env->regs[n]);
  649 + }
  650 + if (n < 24) {
  651 + /* FPA registers. */
  652 + if (gdb_has_xml)
  653 + return 0;
  654 + memset(mem_buf, 0, 12);
  655 + return 12;
  656 + }
  657 + switch (n) {
  658 + case 24:
  659 + /* FPA status register. */
  660 + if (gdb_has_xml)
  661 + return 0;
  662 + GET_REG32(0);
  663 + case 25:
  664 + /* CPSR */
  665 + GET_REG32(cpsr_read(env));
  666 + }
  667 + /* Unknown register. */
  668 + return 0;
697 669 }
698   -#elif defined (TARGET_MIPS)
699   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
700   -{
701   - int i;
702   - uint8_t *ptr;
703 670  
704   - ptr = mem_buf;
705   - for (i = 0; i < 32; i++)
706   - {
707   - *(target_ulong *)ptr = tswapl(env->active_tc.gpr[i]);
708   - ptr += sizeof(target_ulong);
709   - }
  671 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
  672 +{
  673 + uint32_t tmp;
710 674  
711   - *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
712   - ptr += sizeof(target_ulong);
  675 + tmp = ldl_p(mem_buf);
713 676  
714   - *(target_ulong *)ptr = tswapl(env->active_tc.LO[0]);
715   - ptr += sizeof(target_ulong);
  677 + /* Mask out low bit of PC to workaround gdb bugs. This will probably
  678 + cause problems if we ever implement the Jazelle DBX extensions. */
  679 + if (n == 15)
  680 + tmp &= ~1;
716 681  
717   - *(target_ulong *)ptr = tswapl(env->active_tc.HI[0]);
718   - ptr += sizeof(target_ulong);
  682 + if (n < 16) {
  683 + /* Core integer register. */
  684 + env->regs[n] = tmp;
  685 + return 4;
  686 + }
  687 + if (n < 24) { /* 16-23 */
  688 + /* FPA registers (ignored). */
  689 + if (gdb_has_xml)
  690 + return 0;
  691 + return 12;
  692 + }
  693 + switch (n) {
  694 + case 24:
  695 + /* FPA status register (ignored). */
  696 + if (gdb_has_xml)
  697 + return 0;
  698 + return 4;
  699 + case 25:
  700 + /* CPSR */
  701 + cpsr_write (env, tmp, 0xffffffff);
  702 + return 4;
  703 + }
  704 + /* Unknown register. */
  705 + return 0;
  706 +}
719 707  
720   - *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
721   - ptr += sizeof(target_ulong);
  708 +#elif defined (TARGET_M68K)
722 709  
723   - *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
724   - ptr += sizeof(target_ulong);
  710 +#define NUM_CORE_REGS 18
725 711  
726   - *(target_ulong *)ptr = tswapl(env->active_tc.PC);
727   - ptr += sizeof(target_ulong);
  712 +#define GDB_CORE_XML "cf-core.xml"
728 713  
729   - if (env->CP0_Config1 & (1 << CP0C1_FP))
730   - {
731   - for (i = 0; i < 32; i++)
732   - {
733   - if (env->CP0_Status & (1 << CP0St_FR))
734   - *(target_ulong *)ptr = tswapl(env->active_fpu.fpr[i].d);
735   - else
736   - *(target_ulong *)ptr = tswap32(env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);
737   - ptr += sizeof(target_ulong);
738   - }
  714 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
  715 +{
  716 + if (n < 8) {
  717 + /* D0-D7 */
  718 + GET_REG32(env->dregs[n]);
  719 + } else if (n < 16) {
  720 + /* A0-A7 */
  721 + GET_REG32(env->aregs[n - 8]);
  722 + } else {
  723 + switch (n) {
  724 + case 16: GET_REG32(env->sr);
  725 + case 17: GET_REG32(env->pc);
  726 + }
  727 + }
  728 + /* FP registers not included here because they vary between
  729 + ColdFire and m68k. Use XML bits for these. */
  730 + return 0;
  731 +}
739 732  
740   - *(target_ulong *)ptr = (int32_t)tswap32(env->active_fpu.fcr31);
741   - ptr += sizeof(target_ulong);
  733 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
  734 +{
  735 + uint32_t tmp;
742 736  
743   - *(target_ulong *)ptr = (int32_t)tswap32(env->active_fpu.fcr0);
744   - ptr += sizeof(target_ulong);
745   - }
  737 + tmp = ldl_p(mem_buf);
746 738  
747   - /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
748   - *(target_ulong *)ptr = 0;
749   - ptr += sizeof(target_ulong);
  739 + if (n < 8) {
  740 + /* D0-D7 */
  741 + env->dregs[n] = tmp;
  742 + } else if (n < 8) {
  743 + /* A0-A7 */
  744 + env->aregs[n - 8] = tmp;
  745 + } else {
  746 + switch (n) {
  747 + case 16: env->sr = tmp; break;
  748 + case 17: env->pc = tmp; break;
  749 + default: return 0;
  750 + }
  751 + }
  752 + return 4;
  753 +}
  754 +#elif defined (TARGET_MIPS)
750 755  
751   - /* Registers for embedded use, we just pad them. */
752   - for (i = 0; i < 16; i++)
753   - {
754   - *(target_ulong *)ptr = 0;
755   - ptr += sizeof(target_ulong);
756   - }
  756 +#define NUM_CORE_REGS 73
757 757  
758   - /* Processor ID. */
759   - *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
760   - ptr += sizeof(target_ulong);
  758 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
  759 +{
  760 + if (n < 32) {
  761 + GET_REGL(env->active_tc.gpr[n]);
  762 + }
  763 + if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  764 + if (n >= 38 && n < 70) {
  765 + if (env->CP0_Status & (1 << CP0St_FR))
  766 + GET_REGL(env->active_fpu.fpr[n - 38].d);
  767 + else
  768 + GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
  769 + }
  770 + switch (n) {
  771 + case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
  772 + case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
  773 + }
  774 + }
  775 + switch (n) {
  776 + case 32: GET_REGL((int32_t)env->CP0_Status);
  777 + case 33: GET_REGL(env->active_tc.LO[0]);
  778 + case 34: GET_REGL(env->active_tc.HI[0]);
  779 + case 35: GET_REGL(env->CP0_BadVAddr);
  780 + case 36: GET_REGL((int32_t)env->CP0_Cause);
  781 + case 37: GET_REGL(env->active_tc.PC);
  782 + case 72: GET_REGL(0); /* fp */
  783 + case 89: GET_REGL((int32_t)env->CP0_PRid);
  784 + }
  785 + if (n >= 73 && n <= 88) {
  786 + /* 16 embedded regs. */
  787 + GET_REGL(0);
  788 + }
761 789  
762   - return ptr - mem_buf;
  790 + return 0;
763 791 }
764 792  
765 793 /* convert MIPS rounding mode in FCR31 to IEEE library */
... ... @@ -773,202 +801,355 @@ static unsigned int ieee_rm[] =
773 801 #define RESTORE_ROUNDING_MODE \
774 802 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
775 803  
776   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  804 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
777 805 {
778   - int i;
779   - uint8_t *ptr;
780   -
781   - ptr = mem_buf;
782   - for (i = 0; i < 32; i++)
783   - {
784   - env->active_tc.gpr[i] = tswapl(*(target_ulong *)ptr);
785   - ptr += sizeof(target_ulong);
786   - }
787   -
788   - env->CP0_Status = tswapl(*(target_ulong *)ptr);
789   - ptr += sizeof(target_ulong);
  806 + target_ulong tmp;
790 807  
791   - env->active_tc.LO[0] = tswapl(*(target_ulong *)ptr);
792   - ptr += sizeof(target_ulong);
  808 + tmp = ldtul_p(mem_buf);
793 809  
794   - env->active_tc.HI[0] = tswapl(*(target_ulong *)ptr);
795   - ptr += sizeof(target_ulong);
796   -
797   - env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
798   - ptr += sizeof(target_ulong);
799   -
800   - env->CP0_Cause = tswapl(*(target_ulong *)ptr);
801   - ptr += sizeof(target_ulong);
802   -
803   - env->active_tc.PC = tswapl(*(target_ulong *)ptr);
804   - ptr += sizeof(target_ulong);
805   -
806   - if (env->CP0_Config1 & (1 << CP0C1_FP))
807   - {
808   - for (i = 0; i < 32; i++)
809   - {
  810 + if (n < 32) {
  811 + env->active_tc.gpr[n] = tmp;
  812 + return sizeof(target_ulong);
  813 + }
  814 + if (env->CP0_Config1 & (1 << CP0C1_FP)
  815 + && n >= 38 && n < 73) {
  816 + if (n < 70) {
810 817 if (env->CP0_Status & (1 << CP0St_FR))
811   - env->active_fpu.fpr[i].d = tswapl(*(target_ulong *)ptr);
  818 + env->active_fpu.fpr[n - 38].d = tmp;
812 819 else
813   - env->active_fpu.fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
814   - ptr += sizeof(target_ulong);
815   - }
816   -
817   - env->active_fpu.fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
818   - ptr += sizeof(target_ulong);
819   -
820   - /* The remaining registers are assumed to be read-only. */
821   -
822   - /* set rounding mode */
823   - RESTORE_ROUNDING_MODE;
824   -
  820 + env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
  821 + }
  822 + switch (n) {
  823 + case 70:
  824 + env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
  825 + /* set rounding mode */
  826 + RESTORE_ROUNDING_MODE;
825 827 #ifndef CONFIG_SOFTFLOAT
826   - /* no floating point exception for native float */
827   - SET_FP_ENABLE(env->fcr31, 0);
  828 + /* no floating point exception for native float */
  829 + SET_FP_ENABLE(env->active_fpu.fcr31, 0);
828 830 #endif
829   - }
  831 + break;
  832 + case 71: env->active_fpu.fcr0 = tmp; break;
  833 + }
  834 + return sizeof(target_ulong);
  835 + }
  836 + switch (n) {
  837 + case 32: env->CP0_Status = tmp; break;
  838 + case 33: env->active_tc.LO[0] = tmp; break;
  839 + case 34: env->active_tc.HI[0] = tmp; break;
  840 + case 35: env->CP0_BadVAddr = tmp; break;
  841 + case 36: env->CP0_Cause = tmp; break;
  842 + case 37: env->active_tc.PC = tmp; break;
  843 + case 72: /* fp, ignored */ break;
  844 + default:
  845 + if (n > 89)
  846 + return 0;
  847 + /* Other registers are readonly. Ignore writes. */
  848 + break;
  849 + }
  850 +
  851 + return sizeof(target_ulong);
830 852 }
831 853 #elif defined (TARGET_SH4)
832 854  
833 855 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
  856 +/* FIXME: We should use XML for this. */
  857 +
  858 +#define NUM_CORE_REGS 59
834 859  
835   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
  860 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
836 861 {
837   - uint32_t *ptr = (uint32_t *)mem_buf;
838   - int i;
839   -
840   -#define SAVE(x) *ptr++=tswapl(x)
841   - if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
842   - for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
843   - } else {
844   - for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
845   - }
846   - for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
847   - SAVE (env->pc);
848   - SAVE (env->pr);
849   - SAVE (env->gbr);
850   - SAVE (env->vbr);
851   - SAVE (env->mach);
852   - SAVE (env->macl);
853   - SAVE (env->sr);
854   - SAVE (env->fpul);
855   - SAVE (env->fpscr);
856   - for (i = 0; i < 16; i++)
857   - SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
858   - SAVE (env->ssr);
859   - SAVE (env->spc);
860   - for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
861   - for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
862   - return ((uint8_t *)ptr - mem_buf);
  862 + if (n < 8) {
  863 + if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
  864 + GET_REGL(env->gregs[n + 16]);
  865 + } else {
  866 + GET_REGL(env->gregs[n]);
  867 + }
  868 + } else if (n < 16) {
  869 + GET_REGL(env->gregs[n - 8]);
  870 + } else if (n >= 25 && n < 41) {
  871 + GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
  872 + } else if (n >= 43 && n < 51) {
  873 + GET_REGL(env->gregs[n - 43]);
  874 + } else if (n >= 51 && n < 59) {
  875 + GET_REGL(env->gregs[n - (51 - 16)]);
  876 + }
  877 + switch (n) {
  878 + case 16: GET_REGL(env->pc);
  879 + case 17: GET_REGL(env->pr);
  880 + case 18: GET_REGL(env->gbr);
  881 + case 19: GET_REGL(env->vbr);
  882 + case 20: GET_REGL(env->mach);
  883 + case 21: GET_REGL(env->macl);
  884 + case 22: GET_REGL(env->sr);
  885 + case 23: GET_REGL(env->fpul);
  886 + case 24: GET_REGL(env->fpscr);
  887 + case 41: GET_REGL(env->ssr);
  888 + case 42: GET_REGL(env->spc);
  889 + }
  890 +
  891 + return 0;
863 892 }
864 893  
865   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  894 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
866 895 {
867   - uint32_t *ptr = (uint32_t *)mem_buf;
868   - int i;
869   -
870   -#define LOAD(x) (x)=*ptr++;
871   - if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
872   - for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
873   - } else {
874   - for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
875   - }
876   - for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
877   - LOAD (env->pc);
878   - LOAD (env->pr);
879   - LOAD (env->gbr);
880   - LOAD (env->vbr);
881   - LOAD (env->mach);
882   - LOAD (env->macl);
883   - LOAD (env->sr);
884   - LOAD (env->fpul);
885   - LOAD (env->fpscr);
886   - for (i = 0; i < 16; i++)
887   - LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
888   - LOAD (env->ssr);
889   - LOAD (env->spc);
890   - for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
891   - for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
  896 + uint32_t tmp;
  897 +
  898 + tmp = ldl_p(mem_buf);
  899 +
  900 + if (n < 8) {
  901 + if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
  902 + env->gregs[n + 16] = tmp;
  903 + } else {
  904 + env->gregs[n] = tmp;
  905 + }
  906 + return 4;
  907 + } else if (n < 16) {
  908 + env->gregs[n - 8] = tmp;
  909 + return 4;
  910 + } else if (n >= 25 && n < 41) {
  911 + env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
  912 + } else if (n >= 43 && n < 51) {
  913 + env->gregs[n - 43] = tmp;
  914 + return 4;
  915 + } else if (n >= 51 && n < 59) {
  916 + env->gregs[n - (51 - 16)] = tmp;
  917 + return 4;
  918 + }
  919 + switch (n) {
  920 + case 16: env->pc = tmp;
  921 + case 17: env->pr = tmp;
  922 + case 18: env->gbr = tmp;
  923 + case 19: env->vbr = tmp;
  924 + case 20: env->mach = tmp;
  925 + case 21: env->macl = tmp;
  926 + case 22: env->sr = tmp;
  927 + case 23: env->fpul = tmp;
  928 + case 24: env->fpscr = tmp;
  929 + case 41: env->ssr = tmp;
  930 + case 42: env->spc = tmp;
  931 + default: return 0;
  932 + }
  933 +
  934 + return 4;
892 935 }
893 936 #elif defined (TARGET_CRIS)
894 937  
895   -static int cris_save_32 (unsigned char *d, uint32_t value)
  938 +#define NUM_CORE_REGS 49
  939 +
  940 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
896 941 {
897   - *d++ = (value);
898   - *d++ = (value >>= 8);
899   - *d++ = (value >>= 8);
900   - *d++ = (value >>= 8);
901   - return 4;
  942 + uint8_t srs;
  943 +
  944 + srs = env->pregs[PR_SRS];
  945 + if (n < 16) {
  946 + GET_REG32(env->regs[n]);
  947 + }
  948 +
  949 + if (n >= 21 && n < 32) {
  950 + GET_REG32(env->pregs[n - 16]);
  951 + }
  952 + if (n >= 33 && n < 49) {
  953 + GET_REG32(env->sregs[srs][n - 33]);
  954 + }
  955 + switch (n) {
  956 + case 16: GET_REG8(env->pregs[0]);
  957 + case 17: GET_REG8(env->pregs[1]);
  958 + case 18: GET_REG32(env->pregs[2]);
  959 + case 19: GET_REG8(srs);
  960 + case 20: GET_REG16(env->pregs[4]);
  961 + case 32: GET_REG32(env->pc);
  962 + }
  963 +
  964 + return 0;
902 965 }
903   -static int cris_save_16 (unsigned char *d, uint32_t value)
  966 +
  967 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
904 968 {
905   - *d++ = (value);
906   - *d++ = (value >>= 8);
907   - return 2;
  969 + uint32_t tmp;
  970 +
  971 + if (n > 49)
  972 + return 0;
  973 +
  974 + tmp = ldl_p(mem_buf);
  975 +
  976 + if (n < 16) {
  977 + env->regs[n] = tmp;
  978 + }
  979 +
  980 + /* FIXME: Should other regs be writable? */
  981 + switch (n) {
  982 + case 16: return 1;
  983 + case 17: return 1;
  984 + case 18: return 4;
  985 + case 19: return 1;
  986 + case 20: return 2;
  987 + case 32: env->pc = tmp; break;
  988 + }
  989 +
  990 + return 4;
908 991 }
909   -static int cris_save_8 (unsigned char *d, uint32_t value)
  992 +#else
  993 +
  994 +#define NUM_CORE_REGS 0
  995 +
  996 +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
910 997 {
911   - *d++ = (value);
912   - return 1;
  998 + return 0;
913 999 }
914 1000  
915   -/* FIXME: this will bug on archs not supporting unaligned word accesses. */
916   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
  1001 +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
917 1002 {
918   - uint8_t *ptr = mem_buf;
919   - uint8_t srs;
920   - int i;
  1003 + return 0;
  1004 +}
921 1005  
922   - for (i = 0; i < 16; i++)
923   - ptr += cris_save_32 (ptr, env->regs[i]);
  1006 +#endif
924 1007  
925   - srs = env->pregs[PR_SRS];
  1008 +static int num_g_regs = NUM_CORE_REGS;
926 1009  
927   - ptr += cris_save_8 (ptr, env->pregs[0]);
928   - ptr += cris_save_8 (ptr, env->pregs[1]);
929   - ptr += cris_save_32 (ptr, env->pregs[2]);
930   - ptr += cris_save_8 (ptr, srs);
931   - ptr += cris_save_16 (ptr, env->pregs[4]);
  1010 +#ifdef GDB_CORE_XML
  1011 +/* Encode data using the encoding for 'x' packets. */
  1012 +static int memtox(char *buf, const char *mem, int len)
  1013 +{
  1014 + char *p = buf;
  1015 + char c;
  1016 +
  1017 + while (len--) {
  1018 + c = *(mem++);
  1019 + switch (c) {
  1020 + case '#': case '$': case '*': case '}':
  1021 + *(p++) = '}';
  1022 + *(p++) = c ^ 0x20;
  1023 + break;
  1024 + default:
  1025 + *(p++) = c;
  1026 + break;
  1027 + }
  1028 + }
  1029 + return p - buf;
  1030 +}
932 1031  
933   - for (i = 5; i < 16; i++)
934   - ptr += cris_save_32 (ptr, env->pregs[i]);
  1032 +const char *get_feature_xml(CPUState *env, const char *p, const char **newp)
  1033 +{
  1034 + extern const char *const xml_builtin[][2];
  1035 + size_t len;
  1036 + int i;
  1037 + const char *name;
  1038 + static char target_xml[1024];
  1039 +
  1040 + len = 0;
  1041 + while (p[len] && p[len] != ':')
  1042 + len++;
  1043 + *newp = p + len;
  1044 +
  1045 + name = NULL;
  1046 + if (strncmp(p, "target.xml", len) == 0) {
  1047 + /* Generate the XML description for this CPU. */
  1048 + if (!target_xml[0]) {
  1049 + GDBRegisterState *r;
  1050 +
  1051 + sprintf(target_xml,
  1052 + "<?xml version=\"1.0\"?>"
  1053 + "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
  1054 + "<target>"
  1055 + "<xi:include href=\"%s\"/>",
  1056 + GDB_CORE_XML);
  1057 +
  1058 + for (r = env->gdb_regs; r; r = r->next) {
  1059 + strcat(target_xml, "<xi:include href=\"");
  1060 + strcat(target_xml, r->xml);
  1061 + strcat(target_xml, "\"/>");
  1062 + }
  1063 + strcat(target_xml, "</target>");
  1064 + }
  1065 + return target_xml;
  1066 + }
  1067 + for (i = 0; ; i++) {
  1068 + name = xml_builtin[i][0];
  1069 + if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
  1070 + break;
  1071 + }
  1072 + return name ? xml_builtin[i][1] : NULL;
  1073 +}
  1074 +#endif
935 1075  
936   - ptr += cris_save_32 (ptr, env->pc);
  1076 +static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
  1077 +{
  1078 + GDBRegisterState *r;
937 1079  
938   - for (i = 0; i < 16; i++)
939   - ptr += cris_save_32 (ptr, env->sregs[srs][i]);
  1080 + if (reg < NUM_CORE_REGS)
  1081 + return cpu_gdb_read_register(env, mem_buf, reg);
940 1082  
941   - return ((uint8_t *)ptr - mem_buf);
  1083 + for (r = env->gdb_regs; r; r = r->next) {
  1084 + if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
  1085 + return r->get_reg(env, mem_buf, reg - r->base_reg);
  1086 + }
  1087 + }
  1088 + return 0;
942 1089 }
943 1090  
944   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  1091 +static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
945 1092 {
946   - uint32_t *ptr = (uint32_t *)mem_buf;
947   - int i;
  1093 + GDBRegisterState *r;
948 1094  
949   -#define LOAD(x) (x)=*ptr++;
950   - for (i = 0; i < 16; i++) LOAD(env->regs[i]);
951   - LOAD (env->pc);
952   -}
953   -#else
954   -static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
955   -{
  1095 + if (reg < NUM_CORE_REGS)
  1096 + return cpu_gdb_write_register(env, mem_buf, reg);
  1097 +
  1098 + for (r = env->gdb_regs; r; r = r->next) {
  1099 + if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
  1100 + return r->set_reg(env, mem_buf, reg - r->base_reg);
  1101 + }
  1102 + }
956 1103 return 0;
957 1104 }
958 1105  
959   -static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
  1106 +/* Register a supplemental set of CPU registers. If g_pos is nonzero it
  1107 + specifies the first register number and these registers are included in
  1108 + a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
  1109 + gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
  1110 + */
  1111 +
  1112 +void gdb_register_coprocessor(CPUState * env,
  1113 + gdb_reg_cb get_reg, gdb_reg_cb set_reg,
  1114 + int num_regs, const char *xml, int g_pos)
960 1115 {
  1116 + GDBRegisterState *s;
  1117 + GDBRegisterState **p;
  1118 + static int last_reg = NUM_CORE_REGS;
  1119 +
  1120 + s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
  1121 + s->base_reg = last_reg;
  1122 + s->num_regs = num_regs;
  1123 + s->get_reg = get_reg;
  1124 + s->set_reg = set_reg;
  1125 + s->xml = xml;
  1126 + p = &env->gdb_regs;
  1127 + while (*p) {
  1128 + /* Check for duplicates. */
  1129 + if (strcmp((*p)->xml, xml) == 0)
  1130 + return;
  1131 + p = &(*p)->next;
  1132 + }
  1133 + /* Add to end of list. */
  1134 + last_reg += num_regs;
  1135 + *p = s;
  1136 + if (g_pos) {
  1137 + if (g_pos != s->base_reg) {
  1138 + fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
  1139 + "Expected %d got %d\n", xml, g_pos, s->base_reg);
  1140 + } else {
  1141 + num_g_regs = last_reg;
  1142 + }
  1143 + }
961 1144 }
962 1145  
963   -#endif
964   -
965 1146 static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
966 1147 {
967 1148 const char *p;
968 1149 int ch, reg_size, type;
969   - char buf[4096];
970   - uint8_t mem_buf[4096];
971   - uint32_t *registers;
  1150 + char buf[MAX_PACKET_LENGTH];
  1151 + uint8_t mem_buf[MAX_PACKET_LENGTH];
  1152 + uint8_t *registers;
972 1153 target_ulong addr, len;
973 1154  
974 1155 #ifdef DEBUG_GDB
... ... @@ -1073,15 +1254,23 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
1073 1254 }
1074 1255 break;
1075 1256 case 'g':
1076   - reg_size = cpu_gdb_read_registers(env, mem_buf);
1077   - memtohex(buf, mem_buf, reg_size);
  1257 + len = 0;
  1258 + for (addr = 0; addr < num_g_regs; addr++) {
  1259 + reg_size = gdb_read_register(env, mem_buf + len, addr);
  1260 + len += reg_size;
  1261 + }
  1262 + memtohex(buf, mem_buf, len);
1078 1263 put_packet(s, buf);
1079 1264 break;
1080 1265 case 'G':
1081   - registers = (void *)mem_buf;
  1266 + registers = mem_buf;
1082 1267 len = strlen(p) / 2;
1083 1268 hextomem((uint8_t *)registers, p, len);
1084   - cpu_gdb_write_registers(env, mem_buf, len);
  1269 + for (addr = 0; addr < num_g_regs && len > 0; addr++) {
  1270 + reg_size = gdb_write_register(env, registers, addr);
  1271 + len -= reg_size;
  1272 + registers += reg_size;
  1273 + }
1085 1274 put_packet(s, "OK");
1086 1275 break;
1087 1276 case 'm':
... ... @@ -1109,6 +1298,32 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
1109 1298 else
1110 1299 put_packet(s, "OK");
1111 1300 break;
  1301 + case 'p':
  1302 + /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
  1303 + This works, but can be very slow. Anything new enough to
  1304 + understand XML also knows how to use this properly. */
  1305 + if (!gdb_has_xml)
  1306 + goto unknown_command;
  1307 + addr = strtoull(p, (char **)&p, 16);
  1308 + reg_size = gdb_read_register(env, mem_buf, addr);
  1309 + if (reg_size) {
  1310 + memtohex(buf, mem_buf, reg_size);
  1311 + put_packet(s, buf);
  1312 + } else {
  1313 + put_packet(s, "E14");
  1314 + }
  1315 + break;
  1316 + case 'P':
  1317 + if (!gdb_has_xml)
  1318 + goto unknown_command;
  1319 + addr = strtoull(p, (char **)&p, 16);
  1320 + if (*p == '=')
  1321 + p++;
  1322 + reg_size = strlen(p) / 2;
  1323 + hextomem(mem_buf, p, reg_size);
  1324 + gdb_write_register(env, mem_buf, addr);
  1325 + put_packet(s, "OK");
  1326 + break;
1112 1327 case 'Z':
1113 1328 type = strtoul(p, (char **)&p, 16);
1114 1329 if (*p == ',')
... ... @@ -1208,8 +1423,59 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
1208 1423 break;
1209 1424 }
1210 1425 #endif
1211   - /* Fall through. */
  1426 + if (strncmp(p, "Supported", 9) == 0) {
  1427 + sprintf(buf, "PacketSize=%x", MAX_PACKET_LENGTH);
  1428 +#ifdef GDB_CORE_XML
  1429 + strcat(buf, ";qXfer:features:read+");
  1430 +#endif
  1431 + put_packet(s, buf);
  1432 + break;
  1433 + }
  1434 +#ifdef GDB_CORE_XML
  1435 + if (strncmp(p, "Xfer:features:read:", 19) == 0) {
  1436 + const char *xml;
  1437 + target_ulong total_len;
  1438 +
  1439 + gdb_has_xml = 1;
  1440 + p += 19;
  1441 + xml = get_feature_xml(env, p, &p);
  1442 + if (!xml) {
  1443 + sprintf(buf, "E00");
  1444 + put_packet(s, buf);
  1445 + break;
  1446 + }
  1447 +
  1448 + if (*p == ':')
  1449 + p++;
  1450 + addr = strtoul(p, (char **)&p, 16);
  1451 + if (*p == ',')
  1452 + p++;
  1453 + len = strtoul(p, (char **)&p, 16);
  1454 +
  1455 + total_len = strlen(xml);
  1456 + if (addr > total_len) {
  1457 + sprintf(buf, "E00");
  1458 + put_packet(s, buf);
  1459 + break;
  1460 + }
  1461 + if (len > (MAX_PACKET_LENGTH - 5) / 2)
  1462 + len = (MAX_PACKET_LENGTH - 5) / 2;
  1463 + if (len < total_len - addr) {
  1464 + buf[0] = 'm';
  1465 + len = memtox(buf + 1, xml + addr, len);
  1466 + } else {
  1467 + buf[0] = 'l';
  1468 + len = memtox(buf + 1, xml + addr, total_len - addr);
  1469 + }
  1470 + put_packet_binary(s, buf, len + 1);
  1471 + break;
  1472 + }
  1473 +#endif
  1474 + /* Unrecognised 'q' command. */
  1475 + goto unknown_command;
  1476 +
1212 1477 default:
  1478 + unknown_command:
1213 1479 /* put empty packet */
1214 1480 buf[0] = '\0';
1215 1481 put_packet(s, buf);
... ... @@ -1487,6 +1753,7 @@ static void gdb_accept(void *opaque)
1487 1753 memset (s, 0, sizeof (GDBState));
1488 1754 s->env = first_cpu; /* XXX: allow to change CPU */
1489 1755 s->fd = fd;
  1756 + gdb_has_xml = 0;
1490 1757  
1491 1758 gdb_syscall_state = s;
1492 1759  
... ... @@ -1536,7 +1803,9 @@ int gdbserver_start(int port)
1536 1803 #else
1537 1804 static int gdb_chr_can_receive(void *opaque)
1538 1805 {
1539   - return 1;
  1806 + /* We can handle an arbitrarily large amount of data.
  1807 + Pick the maximum packet size, which is as good as anything. */
  1808 + return MAX_PACKET_LENGTH;
1540 1809 }
1541 1810  
1542 1811 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
... ... @@ -1555,6 +1824,7 @@ static void gdb_chr_event(void *opaque, int event)
1555 1824 case CHR_EVENT_RESET:
1556 1825 vm_stop(EXCP_INTERRUPT);
1557 1826 gdb_syscall_state = opaque;
  1827 + gdb_has_xml = 0;
1558 1828 break;
1559 1829 default:
1560 1830 break;
... ...
gdbstub.h
  View file @56aebc8
... ... @@ -15,5 +15,10 @@ int gdbserver_start(int);
15 15 #else
16 16 int gdbserver_start(const char *port);
17 17 #endif
  18 +/* Get or set a register. Returns the size of the register. */
  19 +typedef int (*gdb_reg_cb)(CPUState *env, uint8_t *buf, int reg);
  20 +void gdb_register_coprocessor(CPUState *env,
  21 + gdb_reg_cb get_reg, gdb_reg_cb set_reg,
  22 + int num_regs, const char *xml, int g_pos);
18 23  
19 24 #endif
... ...
target-arm/helper.c
  View file @56aebc8
... ... @@ -173,6 +173,58 @@ void cpu_reset(CPUARMState *env)
173 173 tlb_flush(env, 1);
174 174 }
175 175  
  176 +static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
  177 +{
  178 + int nregs;
  179 +
  180 + /* VFP data registers are always little-endian. */
  181 + nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  182 + if (reg < nregs) {
  183 + stfq_le_p(buf, env->vfp.regs[reg]);
  184 + return 8;
  185 + }
  186 + if (arm_feature(env, ARM_FEATURE_NEON)) {
  187 + /* Aliases for Q regs. */
  188 + nregs += 16;
  189 + if (reg < nregs) {
  190 + stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  191 + stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  192 + return 16;
  193 + }
  194 + }
  195 + switch (reg - nregs) {
  196 + case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  197 + case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  198 + case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  199 + }
  200 + return 0;
  201 +}
  202 +
  203 +static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
  204 +{
  205 + int nregs;
  206 +
  207 + nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  208 + if (reg < nregs) {
  209 + env->vfp.regs[reg] = ldfq_le_p(buf);
  210 + return 8;
  211 + }
  212 + if (arm_feature(env, ARM_FEATURE_NEON)) {
  213 + nregs += 16;
  214 + if (reg < nregs) {
  215 + env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  216 + env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  217 + return 16;
  218 + }
  219 + }
  220 + switch (reg - nregs) {
  221 + case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  222 + case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  223 + case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf); return 4;
  224 + }
  225 + return 0;
  226 +}
  227 +
176 228 CPUARMState *cpu_arm_init(const char *cpu_model)
177 229 {
178 230 CPUARMState *env;
... ... @@ -194,6 +246,16 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
194 246 env->cpu_model_str = cpu_model;
195 247 env->cp15.c0_cpuid = id;
196 248 cpu_reset(env);
  249 + if (arm_feature(env, ARM_FEATURE_NEON)) {
  250 + gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
  251 + 51, "arm-neon.xml", 0);
  252 + } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
  253 + gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
  254 + 35, "arm-vfp3.xml", 0);
  255 + } else if (arm_feature(env, ARM_FEATURE_VFP)) {
  256 + gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
  257 + 19, "arm-vfp.xml", 0);
  258 + }
197 259 return env;
198 260 }
199 261  
... ...
target-m68k/helper.c
  View file @56aebc8
... ... @@ -26,6 +26,7 @@
26 26 #include "cpu.h"
27 27 #include "exec-all.h"
28 28 #include "qemu-common.h"
  29 +#include "gdbstub.h"
29 30  
30 31 #include "helpers.h"
31 32  
... ... @@ -53,6 +54,33 @@ static m68k_def_t m68k_cpu_defs[] = {
53 54 {NULL, 0},
54 55 };
55 56  
  57 +static int fpu_gdb_get_reg(CPUState *env, uint8_t *mem_buf, int n)
  58 +{
  59 + if (n < 8) {
  60 + stfq_p(mem_buf, env->fregs[n]);
  61 + return 8;
  62 + }
  63 + if (n < 11) {
  64 + /* FP control registers (not implemented) */
  65 + memset(mem_buf, 0, 4);
  66 + return 4;
  67 + }
  68 + return 0;
  69 +}
  70 +
  71 +static int fpu_gdb_set_reg(CPUState *env, uint8_t *mem_buf, int n)
  72 +{
  73 + if (n < 8) {
  74 + env->fregs[n] = ldfq_p(mem_buf);
  75 + return 8;
  76 + }
  77 + if (n < 11) {
  78 + /* FP control registers (not implemented) */
  79 + return 4;
  80 + }
  81 + return 0;
  82 +}
  83 +
56 84 static void m68k_set_feature(CPUM68KState *env, int feature)
57 85 {
58 86 env->features |= (1u << feature);
... ... @@ -105,6 +133,11 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name)
105 133 }
106 134  
107 135 register_m68k_insns(env);
  136 + if (m68k_feature (env, M68K_FEATURE_CF_FPU)) {
  137 + gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg,
  138 + 11, "cf-fp.xml", 18);
  139 + }
  140 + /* TODO: Add [E]MAC registers. */
108 141 return 0;
109 142 }
110 143  
... ...