Commit 5592a750b913c859c738eb2774c26632dcac8350
1 parent
7878ff6b
The other half of the mul64 rework. Sorry for the breakage, I committed
an incomplete version of what I tested. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3454 c046a42c-6fe2-441c-8c8c-71466251a162
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3 changed files
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7 additions
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5 deletions
host-utils.c
| @@ -25,6 +25,8 @@ | @@ -25,6 +25,8 @@ | ||
| 25 | 25 | ||
| 26 | #include "vl.h" | 26 | #include "vl.h" |
| 27 | 27 | ||
| 28 | +//#define DEBUG_MULDIV | ||
| 29 | + | ||
| 28 | /* Long integer helpers */ | 30 | /* Long integer helpers */ |
| 29 | static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b) | 31 | static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b) |
| 30 | { | 32 | { |
target-i386/helper.c
| @@ -3724,7 +3724,7 @@ void helper_mulq_EAX_T0(void) | @@ -3724,7 +3724,7 @@ void helper_mulq_EAX_T0(void) | ||
| 3724 | { | 3724 | { |
| 3725 | uint64_t r0, r1; | 3725 | uint64_t r0, r1; |
| 3726 | 3726 | ||
| 3727 | - mulu64(&r1, &r0, EAX, T0); | 3727 | + mulu64(&r0, &r1, EAX, T0); |
| 3728 | EAX = r0; | 3728 | EAX = r0; |
| 3729 | EDX = r1; | 3729 | EDX = r1; |
| 3730 | CC_DST = r0; | 3730 | CC_DST = r0; |
| @@ -3735,7 +3735,7 @@ void helper_imulq_EAX_T0(void) | @@ -3735,7 +3735,7 @@ void helper_imulq_EAX_T0(void) | ||
| 3735 | { | 3735 | { |
| 3736 | uint64_t r0, r1; | 3736 | uint64_t r0, r1; |
| 3737 | 3737 | ||
| 3738 | - muls64(&r1, &r0, EAX, T0); | 3738 | + muls64(&r0, &r1, EAX, T0); |
| 3739 | EAX = r0; | 3739 | EAX = r0; |
| 3740 | EDX = r1; | 3740 | EDX = r1; |
| 3741 | CC_DST = r0; | 3741 | CC_DST = r0; |
| @@ -3746,7 +3746,7 @@ void helper_imulq_T0_T1(void) | @@ -3746,7 +3746,7 @@ void helper_imulq_T0_T1(void) | ||
| 3746 | { | 3746 | { |
| 3747 | uint64_t r0, r1; | 3747 | uint64_t r0, r1; |
| 3748 | 3748 | ||
| 3749 | - muls64(&r1, &r0, T0, T1); | 3749 | + muls64(&r0, &r1, T0, T1); |
| 3750 | T0 = r0; | 3750 | T0 = r0; |
| 3751 | CC_DST = r0; | 3751 | CC_DST = r0; |
| 3752 | CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63)); | 3752 | CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63)); |
target-mips/op.c
| @@ -876,13 +876,13 @@ void op_msubu (void) | @@ -876,13 +876,13 @@ void op_msubu (void) | ||
| 876 | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) | 876 | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) |
| 877 | void op_dmult (void) | 877 | void op_dmult (void) |
| 878 | { | 878 | { |
| 879 | - CALL_FROM_TB4(muls64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1); | 879 | + CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1); |
| 880 | RETURN(); | 880 | RETURN(); |
| 881 | } | 881 | } |
| 882 | 882 | ||
| 883 | void op_dmultu (void) | 883 | void op_dmultu (void) |
| 884 | { | 884 | { |
| 885 | - CALL_FROM_TB4(mulu64, &(env->HI[0][env->current_tc]), &(env->LO[0][env->current_tc]), T0, T1); | 885 | + CALL_FROM_TB4(mulu64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1); |
| 886 | RETURN(); | 886 | RETURN(); |
| 887 | } | 887 | } |
| 888 | #endif | 888 | #endif |