Commit 54fa5af54622a9bd2d4e6988a6e402f60bde3653
1 parent
cc1daa40
more generic IRQ support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1445 c046a42c-6fe2-441c-8c8c-71466251a162
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3 changed files
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46 additions
and
27 deletions
hw/i8259.c
... | ... | @@ -179,6 +179,12 @@ void pic_set_irq(int irq, int level) |
179 | 179 | pic_update_irq(); |
180 | 180 | } |
181 | 181 | |
182 | +/* this function should be used to have the controller context */ | |
183 | +void pic_set_irq_new(void *opaque, int irq, int level) | |
184 | +{ | |
185 | + pic_set_irq(irq, level); | |
186 | +} | |
187 | + | |
182 | 188 | /* acknowledge interrupt 'irq' */ |
183 | 189 | static inline void pic_intack(PicState *s, int irq) |
184 | 190 | { | ... | ... |
hw/openpic.c
... | ... | @@ -320,8 +320,9 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
320 | 320 | } |
321 | 321 | } |
322 | 322 | |
323 | -void openpic_set_irq(openpic_t *opp, int n_IRQ, int level) | |
323 | +void openpic_set_irq(void *opaque, int n_IRQ, int level) | |
324 | 324 | { |
325 | + openpic_t *opp = opaque; | |
325 | 326 | IRQ_src_t *src; |
326 | 327 | |
327 | 328 | src = &opp->src[n_IRQ]; | ... | ... |
vl.h
... | ... | @@ -443,6 +443,24 @@ int qcow_compress_cluster(BlockDriverState *bs, int64_t sector_num, |
443 | 443 | const uint8_t *buf); |
444 | 444 | |
445 | 445 | #ifndef QEMU_TOOL |
446 | + | |
447 | +typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, | |
448 | + int boot_device, | |
449 | + DisplayState *ds, const char **fd_filename, int snapshot, | |
450 | + const char *kernel_filename, const char *kernel_cmdline, | |
451 | + const char *initrd_filename); | |
452 | + | |
453 | +typedef struct QEMUMachine { | |
454 | + const char *name; | |
455 | + const char *desc; | |
456 | + QEMUMachineInitFunc *init; | |
457 | + struct QEMUMachine *next; | |
458 | +} QEMUMachine; | |
459 | + | |
460 | +int qemu_register_machine(QEMUMachine *m); | |
461 | + | |
462 | +typedef void SetIRQFunc(void *opaque, int irq_num, int level); | |
463 | + | |
446 | 464 | /* ISA bus */ |
447 | 465 | |
448 | 466 | extern target_phys_addr_t isa_mem_base; |
... | ... | @@ -527,16 +545,21 @@ void pci_bios_init(void); |
527 | 545 | void pci_info(void); |
528 | 546 | |
529 | 547 | /* temporary: will be moved in platform specific file */ |
548 | +void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque); | |
530 | 549 | PCIBus *pci_prep_init(void); |
531 | -struct openpic_t; | |
532 | -void pci_pmac_set_openpic(PCIBus *bus, struct openpic_t *openpic); | |
550 | +PCIBus *pci_grackle_init(uint32_t base); | |
533 | 551 | PCIBus *pci_pmac_init(void); |
534 | 552 | |
535 | 553 | /* openpic.c */ |
536 | 554 | typedef struct openpic_t openpic_t; |
537 | -void openpic_set_irq (openpic_t *opp, int n_IRQ, int level); | |
555 | +void openpic_set_irq(void *opaque, int n_IRQ, int level); | |
538 | 556 | openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus); |
539 | 557 | |
558 | +/* heathrow_pic.c */ | |
559 | +typedef struct HeathrowPICS HeathrowPICS; | |
560 | +void heathrow_pic_set_irq(void *opaque, int num, int level); | |
561 | +HeathrowPICS *heathrow_pic_init(int *pmem_index); | |
562 | + | |
540 | 563 | /* vga.c */ |
541 | 564 | |
542 | 565 | #define VGA_RAM_SIZE (4096 * 1024) |
... | ... | @@ -587,10 +610,11 @@ extern BlockDriverState *bs_table[MAX_DISKS]; |
587 | 610 | |
588 | 611 | void isa_ide_init(int iobase, int iobase2, int irq, |
589 | 612 | BlockDriverState *hd0, BlockDriverState *hd1); |
590 | -void pci_ide_init(PCIBus *bus, BlockDriverState **hd_table); | |
613 | +void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table, | |
614 | + int secondary_ide_enabled); | |
591 | 615 | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table); |
592 | 616 | int pmac_ide_init (BlockDriverState **hd_table, |
593 | - openpic_t *openpic, int irq); | |
617 | + SetIRQFunc *set_irq, void *irq_opaque, int irq); | |
594 | 618 | |
595 | 619 | /* sb16.c */ |
596 | 620 | void SB16_init (void); |
... | ... | @@ -655,6 +679,7 @@ ParallelState *parallel_init(int base, int irq, CharDriverState *chr); |
655 | 679 | /* i8259.c */ |
656 | 680 | |
657 | 681 | void pic_set_irq(int irq, int level); |
682 | +void pic_set_irq_new(void *opaque, int irq, int level); | |
658 | 683 | void pic_init(void); |
659 | 684 | uint32_t pic_intack_read(CPUState *env); |
660 | 685 | void pic_info(void); |
... | ... | @@ -676,24 +701,13 @@ int pit_get_gate(PITState *pit, int channel); |
676 | 701 | int pit_get_out(PITState *pit, int channel, int64_t current_time); |
677 | 702 | |
678 | 703 | /* pc.c */ |
679 | -void pc_init(int ram_size, int vga_ram_size, int boot_device, | |
680 | - DisplayState *ds, const char **fd_filename, int snapshot, | |
681 | - const char *kernel_filename, const char *kernel_cmdline, | |
682 | - const char *initrd_filename); | |
704 | +extern QEMUMachine pc_machine; | |
683 | 705 | |
684 | 706 | /* ppc.c */ |
685 | -void ppc_init (int ram_size, int vga_ram_size, int boot_device, | |
686 | - DisplayState *ds, const char **fd_filename, int snapshot, | |
687 | - const char *kernel_filename, const char *kernel_cmdline, | |
688 | - const char *initrd_filename); | |
689 | -void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device, | |
690 | - DisplayState *ds, const char **fd_filename, int snapshot, | |
691 | - const char *kernel_filename, const char *kernel_cmdline, | |
692 | - const char *initrd_filename); | |
693 | -void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, | |
694 | - DisplayState *ds, const char **fd_filename, int snapshot, | |
695 | - const char *kernel_filename, const char *kernel_cmdline, | |
696 | - const char *initrd_filename); | |
707 | +extern QEMUMachine prep_machine; | |
708 | +extern QEMUMachine core99_machine; | |
709 | +extern QEMUMachine heathrow_machine; | |
710 | + | |
697 | 711 | #ifdef TARGET_PPC |
698 | 712 | ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
699 | 713 | #endif |
... | ... | @@ -702,12 +716,10 @@ void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
702 | 716 | extern CPUWriteMemoryFunc *PPC_io_write[]; |
703 | 717 | extern CPUReadMemoryFunc *PPC_io_read[]; |
704 | 718 | extern int prep_enabled; |
719 | +void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); | |
705 | 720 | |
706 | 721 | /* sun4m.c */ |
707 | -void sun4m_init(int ram_size, int vga_ram_size, int boot_device, | |
708 | - DisplayState *ds, const char **fd_filename, int snapshot, | |
709 | - const char *kernel_filename, const char *kernel_cmdline, | |
710 | - const char *initrd_filename); | |
722 | +extern QEMUMachine sun4m_machine; | |
711 | 723 | uint32_t iommu_translate(uint32_t addr); |
712 | 724 | |
713 | 725 | /* iommu.c */ |
... | ... | @@ -809,7 +821,7 @@ void adb_mouse_init(ADBBusState *bus); |
809 | 821 | /* cuda.c */ |
810 | 822 | |
811 | 823 | extern ADBBusState adb_bus; |
812 | -int cuda_init(openpic_t *openpic, int irq); | |
824 | +int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq); | |
813 | 825 | |
814 | 826 | #endif /* defined(QEMU_TOOL) */ |
815 | 827 | ... | ... |