gwj / at91sam9263 · Commits

Commit 54843a58610e0ef43200d0e23a057589876a4b6f

Authored by aurel32
1 parent 15824571

target-ppc: use the new rotr/rotri instructions 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5608 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 47 additions and 59 deletions
target-ppc/translate.c
  View file @54843a5
@@ -1673,20 +1673,21 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1673,20 +1673,21 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1673 target_ulong mask; 1673 target_ulong mask;
1674 1674
1675 t0 = tcg_temp_new(TCG_TYPE_TL); 1675 t0 = tcg_temp_new(TCG_TYPE_TL);
1676 - t1 = tcg_temp_new(TCG_TYPE_TL);  
1677 - if (likely(sh == 0)) {  
1678 - tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);  
1679 - } else {  
1680 - tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);  
1681 - tcg_gen_shli_tl(t0, t1, sh);  
1682 - tcg_gen_shri_tl(t1, t1, 32 - sh);  
1683 - tcg_gen_or_tl(t0, t0, t1);  
1684 - } 1676 +#if defined(TARGET_PPC64)
  1677 + t1 = tcg_temp_new(TCG_TYPE_I32);
  1678 + tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
  1679 + tcg_gen_rotli_i32(t1, t1, sh);
  1680 + tcg_gen_extu_i32_i64(t0, t1);
  1681 + tcg_temp_free(t1);
  1682 +#else
  1683 + tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
  1684 +#endif
1685 #if defined(TARGET_PPC64) 1685 #if defined(TARGET_PPC64)
1686 mb += 32; 1686 mb += 32;
1687 me += 32; 1687 me += 32;
1688 #endif 1688 #endif
1689 mask = MASK(mb, me); 1689 mask = MASK(mb, me);
  1690 + t1 = tcg_temp_new(TCG_TYPE_TL);
1690 tcg_gen_andi_tl(t0, t0, mask); 1691 tcg_gen_andi_tl(t0, t0, mask);
1691 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); 1692 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1692 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 1693 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
@@ -1723,16 +1724,15 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1723,16 +1724,15 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1723 tcg_temp_free(t0); 1724 tcg_temp_free(t0);
1724 } else { 1725 } else {
1725 TCGv t0 = tcg_temp_new(TCG_TYPE_TL); 1726 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1726 - if (likely(sh != 0)) {  
1727 - TCGv t1 = tcg_temp_new(TCG_TYPE_TL);  
1728 - tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);  
1729 - tcg_gen_shli_tl(t1, t0, sh);  
1730 - tcg_gen_shri_tl(t0, t0, 32 - sh);  
1731 - tcg_gen_or_tl(t0, t0, t1);  
1732 - tcg_temp_free(t1);  
1733 - } else {  
1734 - tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);  
1735 - } 1727 +#if defined(TARGET_PPC64)
  1728 + TCGv t1 = tcg_temp_new(TCG_TYPE_I32);
  1729 + tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
  1730 + tcg_gen_rotli_i32(t1, t1, sh);
  1731 + tcg_gen_extu_i32_i64(t0, t1);
  1732 + tcg_temp_free(t1);
  1733 +#else
  1734 + tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
  1735 +#endif
1736 #if defined(TARGET_PPC64) 1736 #if defined(TARGET_PPC64)
1737 mb += 32; 1737 mb += 32;
1738 me += 32; 1738 me += 32;
@@ -1747,31 +1747,37 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1747,31 +1747,37 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1747 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) 1747 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1748 { 1748 {
1749 uint32_t mb, me; 1749 uint32_t mb, me;
1750 - TCGv t0, t1, t2; 1750 + TCGv t0;
  1751 +#if defined(TARGET_PPC64)
  1752 + TCGv t1, t2;
  1753 +#endif
1751 1754
1752 mb = MB(ctx->opcode); 1755 mb = MB(ctx->opcode);
1753 me = ME(ctx->opcode); 1756 me = ME(ctx->opcode);
1754 t0 = tcg_temp_new(TCG_TYPE_TL); 1757 t0 = tcg_temp_new(TCG_TYPE_TL);
1755 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); 1758 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1756 - t1 = tcg_temp_new(TCG_TYPE_TL);  
1757 - tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);  
1758 - t2 = tcg_temp_new(TCG_TYPE_TL);  
1759 - tcg_gen_shl_tl(t2, t1, t0);  
1760 - tcg_gen_subfi_tl(t0, 32, t0);  
1761 - tcg_gen_shr_tl(t1, t1, t0);  
1762 - tcg_temp_free(t0);  
1763 - tcg_gen_or_tl(t2, t2, t1); 1759 +#if defined(TARGET_PPC64)
  1760 + t1 = tcg_temp_new(TCG_TYPE_I32);
  1761 + t2 = tcg_temp_new(TCG_TYPE_I32);
  1762 + tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
  1763 + tcg_gen_trunc_i64_i32(t2, t0);
  1764 + tcg_gen_rotl_i32(t1, t1, t2);
  1765 + tcg_gen_extu_i32_i64(t0, t1);
1764 tcg_temp_free(t1); 1766 tcg_temp_free(t1);
  1767 + tcg_temp_free(t2);
  1768 +#else
  1769 + tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
  1770 +#endif
1765 if (unlikely(mb != 0 || me != 31)) { 1771 if (unlikely(mb != 0 || me != 31)) {
1766 #if defined(TARGET_PPC64) 1772 #if defined(TARGET_PPC64)
1767 mb += 32; 1773 mb += 32;
1768 me += 32; 1774 me += 32;
1769 #endif 1775 #endif
1770 - tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t2, MASK(mb, me)); 1776 + tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1771 } else { 1777 } else {
1772 - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t2); 1778 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1773 } 1779 }
1774 - tcg_temp_free(t2); 1780 + tcg_temp_free(t0);
1775 if (unlikely(Rc(ctx->opcode) != 0)) 1781 if (unlikely(Rc(ctx->opcode) != 0))
1776 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1782 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1777 } 1783 }
@@ -1817,17 +1823,9 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, @@ -1817,17 +1823,9 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1817 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); 1823 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1818 } else { 1824 } else {
1819 TCGv t0 = tcg_temp_new(TCG_TYPE_TL); 1825 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1820 - if (likely(sh != 0)) {  
1821 - TCGv t1 = tcg_temp_new(TCG_TYPE_TL);  
1822 - tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);  
1823 - tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);  
1824 - tcg_gen_or_tl(t0, t0, t1);  
1825 - tcg_temp_free(t1);  
1826 - } else {  
1827 - tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);  
1828 - } 1826 + tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1829 if (likely(mb == 0 && me == 63)) { 1827 if (likely(mb == 0 && me == 63)) {
1830 - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); 1828 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1831 } else { 1829 } else {
1832 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); 1830 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1833 } 1831 }
@@ -1870,23 +1868,19 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04); @@ -1870,23 +1868,19 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04);
1870 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, 1868 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1871 uint32_t me) 1869 uint32_t me)
1872 { 1870 {
1873 - TCGv t0, t1; 1871 + TCGv t0;
1874 1872
1875 mb = MB(ctx->opcode); 1873 mb = MB(ctx->opcode);
1876 me = ME(ctx->opcode); 1874 me = ME(ctx->opcode);
1877 t0 = tcg_temp_new(TCG_TYPE_TL); 1875 t0 = tcg_temp_new(TCG_TYPE_TL);
1878 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); 1876 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1879 - t1 = tcg_temp_new(TCG_TYPE_TL);  
1880 - tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0);  
1881 - tcg_gen_subfi_tl(t0, 64, t0);  
1882 - tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);  
1883 - tcg_gen_or_tl(t1, t1, t0);  
1884 - tcg_temp_free(t0); 1877 + tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1885 if (unlikely(mb != 0 || me != 63)) { 1878 if (unlikely(mb != 0 || me != 63)) {
1886 - tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t1, MASK(mb, me));  
1887 - } else  
1888 - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);  
1889 - tcg_temp_free(t1); 1879 + tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
  1880 + } else {
  1881 + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
  1882 + }
  1883 + tcg_temp_free(t0);
1890 if (unlikely(Rc(ctx->opcode) != 0)) 1884 if (unlikely(Rc(ctx->opcode) != 0))
1891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1885 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1892 } 1886 }
@@ -1924,14 +1918,8 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) @@ -1924,14 +1918,8 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1924 target_ulong mask; 1918 target_ulong mask;
1925 1919
1926 t0 = tcg_temp_new(TCG_TYPE_TL); 1920 t0 = tcg_temp_new(TCG_TYPE_TL);
  1921 + tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1927 t1 = tcg_temp_new(TCG_TYPE_TL); 1922 t1 = tcg_temp_new(TCG_TYPE_TL);
1928 - if (likely(sh == 0)) {  
1929 - tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);  
1930 - } else {  
1931 - tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);  
1932 - tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);  
1933 - tcg_gen_or_tl(t0, t0, t1);  
1934 - }  
1935 mask = MASK(mb, me); 1923 mask = MASK(mb, me);
1936 tcg_gen_andi_tl(t0, t0, mask); 1924 tcg_gen_andi_tl(t0, t0, mask);
1937 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); 1925 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);