gwj / at91sam9263 · Commits

Commit 538f368612565f7c7672145c31e87f1d3d02d545

Authored by Nitin A Kamble
Committed by Anthony Liguori
1 parent ef768138

QEMU KVM: i386: Fix the cpu reset state 

As per the IA32 processor manual, the accessed bit is set to 1 in the
processor state after reset. qemu pc cpu_reset code was missing this
accessed bit setting.

Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Inline Side-by-side
Showing 1 changed file with 12 additions and 6 deletions
target-i386/helper.c
  View file @538f368
@@ -496,17 +496,23 @@ void cpu_reset(CPUX86State *env) @@ -496,17 +496,23 @@ void cpu_reset(CPUX86State *env)
496 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 496 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
497 497
498 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 498 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
499 - DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK); 499 + DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
  500 + DESC_R_MASK | DESC_A_MASK);
500 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 501 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
501 - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); 502 + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
  503 + DESC_A_MASK);
502 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 504 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
503 - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); 505 + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
  506 + DESC_A_MASK);
504 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 507 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
505 - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); 508 + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
  509 + DESC_A_MASK);
506 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 510 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
507 - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); 511 + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
  512 + DESC_A_MASK);
508 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 513 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
509 - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); 514 + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
  515 + DESC_A_MASK);
510 516
511 env->eip = 0xfff0; 517 env->eip = 0xfff0;
512 env->regs[R_EDX] = env->cpuid_version; 518 env->regs[R_EDX] = env->cpuid_version;