Commit 537730b956572a9e32adfa2e18164e8234594c08
1 parent
edf779ff
zero offset optimisation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@635 c046a42c-6fe2-441c-8c8c-71466251a162
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4 additions
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2 deletions
target-arm/translate.c
| @@ -279,7 +279,8 @@ static inline void gen_add_data_offset(DisasContext *s, unsigned int insn) | @@ -279,7 +279,8 @@ static inline void gen_add_data_offset(DisasContext *s, unsigned int insn) | ||
| 279 | val = insn & 0xfff; | 279 | val = insn & 0xfff; |
| 280 | if (!(insn & (1 << 23))) | 280 | if (!(insn & (1 << 23))) |
| 281 | val = -val; | 281 | val = -val; |
| 282 | - gen_op_addl_T1_im(val); | 282 | + if (val != 0) |
| 283 | + gen_op_addl_T1_im(val); | ||
| 283 | } else { | 284 | } else { |
| 284 | /* shift/register */ | 285 | /* shift/register */ |
| 285 | rm = (insn) & 0xf; | 286 | rm = (insn) & 0xf; |
| @@ -304,7 +305,8 @@ static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn) | @@ -304,7 +305,8 @@ static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn) | ||
| 304 | val = (insn & 0xf) | ((insn >> 4) & 0xf0); | 305 | val = (insn & 0xf) | ((insn >> 4) & 0xf0); |
| 305 | if (!(insn & (1 << 23))) | 306 | if (!(insn & (1 << 23))) |
| 306 | val = -val; | 307 | val = -val; |
| 307 | - gen_op_addl_T1_im(val); | 308 | + if (val != 0) |
| 309 | + gen_op_addl_T1_im(val); | ||
| 308 | } else { | 310 | } else { |
| 309 | /* register */ | 311 | /* register */ |
| 310 | rm = (insn) & 0xf; | 312 | rm = (insn) & 0xf; |