Commit 52781543adc9590fee28d77b15634795a096fc86
1 parent
23cde8bb
On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64
Avoids nasty warnings about flush_icache_range from gcc4 and inability to compile [cpu-]exec.c with gcc3 and -O, also the function is much too large to be candidate for inlining anyway. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
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31 additions
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35 deletions
exec-all.h
| ... | ... | @@ -191,43 +191,8 @@ extern int code_gen_max_blocks; |
| 191 | 191 | #if defined(USE_DIRECT_JUMP) |
| 192 | 192 | |
| 193 | 193 | #if defined(__powerpc__) |
| 194 | -#if defined(__powerpc64__) | |
| 195 | 194 | extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
| 196 | 195 | #define tb_set_jmp_target1 ppc_tb_set_jmp_target |
| 197 | -#else | |
| 198 | -static inline void flush_icache_range(unsigned long start, unsigned long stop); | |
| 199 | -static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) | |
| 200 | -{ | |
| 201 | - /* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */ | |
| 202 | - uint32_t *ptr; | |
| 203 | - long disp = addr - jmp_addr; | |
| 204 | - unsigned long patch_size; | |
| 205 | - | |
| 206 | - ptr = (uint32_t *)jmp_addr; | |
| 207 | - | |
| 208 | - if ((disp << 6) >> 6 != disp) { | |
| 209 | - ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */ | |
| 210 | - ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */ | |
| 211 | - ptr[2] = 0x7c0903a6; /* mtctr 0 */ | |
| 212 | - ptr[3] = 0x4e800420; /* brctr */ | |
| 213 | - patch_size = 16; | |
| 214 | - } else { | |
| 215 | - /* patch the branch destination */ | |
| 216 | - if (disp != 16) { | |
| 217 | - *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */ | |
| 218 | - patch_size = 4; | |
| 219 | - } else { | |
| 220 | - ptr[0] = 0x60000000; /* nop */ | |
| 221 | - ptr[1] = 0x60000000; | |
| 222 | - ptr[2] = 0x60000000; | |
| 223 | - ptr[3] = 0x60000000; | |
| 224 | - patch_size = 16; | |
| 225 | - } | |
| 226 | - } | |
| 227 | - /* flush icache */ | |
| 228 | - flush_icache_range(jmp_addr, jmp_addr + patch_size); | |
| 229 | -} | |
| 230 | -#endif | |
| 231 | 196 | #elif defined(__i386__) || defined(__x86_64__) |
| 232 | 197 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
| 233 | 198 | { | ... | ... |
tcg/ppc/tcg-target.c
| ... | ... | @@ -1015,6 +1015,37 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, |
| 1015 | 1015 | tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index); |
| 1016 | 1016 | } |
| 1017 | 1017 | |
| 1018 | +void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) | |
| 1019 | +{ | |
| 1020 | + uint32_t *ptr; | |
| 1021 | + long disp = addr - jmp_addr; | |
| 1022 | + unsigned long patch_size; | |
| 1023 | + | |
| 1024 | + ptr = (uint32_t *)jmp_addr; | |
| 1025 | + | |
| 1026 | + if ((disp << 6) >> 6 != disp) { | |
| 1027 | + ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */ | |
| 1028 | + ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */ | |
| 1029 | + ptr[2] = 0x7c0903a6; /* mtctr 0 */ | |
| 1030 | + ptr[3] = 0x4e800420; /* brctr */ | |
| 1031 | + patch_size = 16; | |
| 1032 | + } else { | |
| 1033 | + /* patch the branch destination */ | |
| 1034 | + if (disp != 16) { | |
| 1035 | + *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */ | |
| 1036 | + patch_size = 4; | |
| 1037 | + } else { | |
| 1038 | + ptr[0] = 0x60000000; /* nop */ | |
| 1039 | + ptr[1] = 0x60000000; | |
| 1040 | + ptr[2] = 0x60000000; | |
| 1041 | + ptr[3] = 0x60000000; | |
| 1042 | + patch_size = 16; | |
| 1043 | + } | |
| 1044 | + } | |
| 1045 | + /* flush icache */ | |
| 1046 | + flush_icache_range(jmp_addr, jmp_addr + patch_size); | |
| 1047 | +} | |
| 1048 | + | |
| 1018 | 1049 | static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
| 1019 | 1050 | const int *const_args) |
| 1020 | 1051 | { | ... | ... |