gwj / at91sam9263 · Commits

Commit 527067d89285f3d78b4d05ec24cab2c786a2d7fd

Authored by blueswir1
1 parent 6176a26d

Fix TCGv size mismatches 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5593 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 21 additions and 19 deletions
target-sparc/translate.c
  View file @527067d
@@ -297,7 +297,7 @@ static inline void gen_cc_NZ_icc(TCGv dst) @@ -297,7 +297,7 @@ static inline void gen_cc_NZ_icc(TCGv dst)
297 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); 297 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
298 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); 298 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
299 gen_set_label(l1); 299 gen_set_label(l1);
300 - tcg_gen_ext_i32_tl(r_temp, dst); 300 + tcg_gen_ext32s_tl(r_temp, dst);
301 tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2); 301 tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
302 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); 302 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
303 gen_set_label(l2); 303 gen_set_label(l2);
@@ -745,8 +745,8 @@ static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) @@ -745,8 +745,8 @@ static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
745 r_temp = tcg_temp_new(TCG_TYPE_I64); 745 r_temp = tcg_temp_new(TCG_TYPE_I64);
746 r_temp2 = tcg_temp_new(TCG_TYPE_I64); 746 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
747 747
748 - tcg_gen_extu_i32_i64(r_temp, src2);  
749 - tcg_gen_extu_i32_i64(r_temp2, src1); 748 + tcg_gen_extu_tl_i64(r_temp, src2);
  749 + tcg_gen_extu_tl_i64(r_temp2, src1);
750 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); 750 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
751 751
752 tcg_gen_shri_i64(r_temp, r_temp2, 32); 752 tcg_gen_shri_i64(r_temp, r_temp2, 32);
@@ -768,8 +768,8 @@ static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) @@ -768,8 +768,8 @@ static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
768 r_temp = tcg_temp_new(TCG_TYPE_I64); 768 r_temp = tcg_temp_new(TCG_TYPE_I64);
769 r_temp2 = tcg_temp_new(TCG_TYPE_I64); 769 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
770 770
771 - tcg_gen_ext_i32_i64(r_temp, src2);  
772 - tcg_gen_ext_i32_i64(r_temp2, src1); 771 + tcg_gen_ext_tl_i64(r_temp, src2);
  772 + tcg_gen_ext_tl_i64(r_temp2, src1);
773 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); 773 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
774 774
775 tcg_gen_shri_i64(r_temp, r_temp2, 32); 775 tcg_gen_shri_i64(r_temp, r_temp2, 32);
@@ -2204,9 +2204,10 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2204,9 +2204,10 @@ static void disas_sparc_insn(DisasContext * dc)
2204 r_tsptr = tcg_temp_new(TCG_TYPE_PTR); 2204 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2205 tcg_gen_ld_ptr(r_tsptr, cpu_env, 2205 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2206 offsetof(CPUState, tsptr)); 2206 offsetof(CPUState, tsptr));
2207 - tcg_gen_ld_tl(cpu_tmp0, r_tsptr, 2207 + tcg_gen_ld_tl(cpu_tmp32, r_tsptr,
2208 offsetof(trap_state, tpc)); 2208 offsetof(trap_state, tpc));
2209 tcg_temp_free(r_tsptr); 2209 tcg_temp_free(r_tsptr);
  2210 + tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2210 } 2211 }
2211 break; 2212 break;
2212 case 1: // tnpc 2213 case 1: // tnpc
@@ -2314,7 +2315,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2314,7 +2315,7 @@ static void disas_sparc_insn(DisasContext * dc)
2314 CHECK_IU_FEATURE(dc, HYPV); 2315 CHECK_IU_FEATURE(dc, HYPV);
2315 if (!hypervisor(dc)) 2316 if (!hypervisor(dc))
2316 goto priv_insn; 2317 goto priv_insn;
2317 - tcg_gen_ext_i32_tl(cpu_tmp0, cpu_ssr); 2318 + tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
2318 break; 2319 break;
2319 case 31: // ver 2320 case 31: // ver
2320 tcg_gen_mov_tl(cpu_tmp0, cpu_ver); 2321 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
@@ -3027,7 +3028,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3027,7 +3028,7 @@ static void disas_sparc_insn(DisasContext * dc)
3027 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f); 3028 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
3028 } else { 3029 } else {
3029 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); 3030 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3030 - tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); 3031 + tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3031 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f); 3032 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
3032 } 3033 }
3033 } else { /* register */ 3034 } else { /* register */
@@ -3039,7 +3040,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3039,7 +3040,7 @@ static void disas_sparc_insn(DisasContext * dc)
3039 } else { 3040 } else {
3040 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); 3041 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3041 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); 3042 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3042 - tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); 3043 + tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3043 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); 3044 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
3044 } 3045 }
3045 } 3046 }
@@ -3425,7 +3426,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3425,7 +3426,8 @@ static void disas_sparc_insn(DisasContext * dc)
3425 r_tsptr = tcg_temp_new(TCG_TYPE_PTR); 3426 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3426 tcg_gen_ld_ptr(r_tsptr, cpu_env, 3427 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3427 offsetof(CPUState, tsptr)); 3428 offsetof(CPUState, tsptr));
3428 - tcg_gen_st_i32(cpu_tmp0, r_tsptr, 3429 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
  3430 + tcg_gen_st_i32(cpu_tmp32, r_tsptr,
3429 offsetof(trap_state, tt)); 3431 offsetof(trap_state, tt));
3430 tcg_temp_free(r_tsptr); 3432 tcg_temp_free(r_tsptr);
3431 } 3433 }
@@ -3506,7 +3508,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3506,7 +3508,7 @@ static void disas_sparc_insn(DisasContext * dc)
3506 CHECK_IU_FEATURE(dc, HYPV); 3508 CHECK_IU_FEATURE(dc, HYPV);
3507 if (!hypervisor(dc)) 3509 if (!hypervisor(dc))
3508 goto priv_insn; 3510 goto priv_insn;
3509 - tcg_gen_trunc_tl_i32(cpu_ssr, cpu_tmp0); 3511 + tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
3510 break; 3512 break;
3511 default: 3513 default:
3512 goto illegal_insn; 3514 goto illegal_insn;
@@ -4304,9 +4306,9 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4304,9 +4306,9 @@ static void disas_sparc_insn(DisasContext * dc)
4304 CHECK_IU_FEATURE(dc, SWAP); 4306 CHECK_IU_FEATURE(dc, SWAP);
4305 gen_movl_reg_TN(rd, cpu_val); 4307 gen_movl_reg_TN(rd, cpu_val);
4306 gen_address_mask(dc, cpu_addr); 4308 gen_address_mask(dc, cpu_addr);
4307 - tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); 4309 + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4308 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); 4310 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4309 - tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32); 4311 + tcg_gen_mov_tl(cpu_val, cpu_tmp0);
4310 break; 4312 break;
4311 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 4313 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4312 case 0x10: /* load word alternate */ 4314 case 0x10: /* load word alternate */
@@ -4451,7 +4453,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4451,7 +4453,8 @@ static void disas_sparc_insn(DisasContext * dc)
4451 switch (xop) { 4453 switch (xop) {
4452 case 0x20: /* load fpreg */ 4454 case 0x20: /* load fpreg */
4453 gen_address_mask(dc, cpu_addr); 4455 gen_address_mask(dc, cpu_addr);
4454 - tcg_gen_qemu_ld32u(cpu_fpr[rd], cpu_addr, dc->mem_idx); 4456 + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
  4457 + tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
4455 break; 4458 break;
4456 case 0x21: /* ldfsr, V9 ldxfsr */ 4459 case 0x21: /* ldfsr, V9 ldxfsr */
4457 #ifdef TARGET_SPARC64 4460 #ifdef TARGET_SPARC64
@@ -4590,7 +4593,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4590,7 +4593,8 @@ static void disas_sparc_insn(DisasContext * dc)
4590 switch (xop) { 4593 switch (xop) {
4591 case 0x24: /* store fpreg */ 4594 case 0x24: /* store fpreg */
4592 gen_address_mask(dc, cpu_addr); 4595 gen_address_mask(dc, cpu_addr);
4593 - tcg_gen_qemu_st32(cpu_fpr[rd], cpu_addr, dc->mem_idx); 4596 + tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
  4597 + tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
4594 break; 4598 break;
4595 case 0x25: /* stfsr, V9 stxfsr */ 4599 case 0x25: /* stfsr, V9 stxfsr */
4596 #ifdef TARGET_SPARC64 4600 #ifdef TARGET_SPARC64
@@ -4598,10 +4602,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4598,10 +4602,8 @@ static void disas_sparc_insn(DisasContext * dc)
4598 tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); 4602 tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
4599 if (rd == 1) 4603 if (rd == 1)
4600 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); 4604 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4601 - else {  
4602 - tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp64);  
4603 - tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);  
4604 - } 4605 + else
  4606 + tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
4605 #else 4607 #else
4606 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); 4608 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
4607 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); 4609 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);