gwj / at91sam9263 · Commits

Commit 513f789f6b187faf1fd533dc6972bbfa021c4381

Authored by blueswir1
1 parent 7e12f656

Use firmware configuration instead of NVRAM (initial patch by Aurelien Jarno) 

Use firmware configuration device for boot device, kernel, initrd and
kernel command line parameters on PPC, Sparc32 and Sparc64.

Update OpenBIOS images to r479 which supports the change.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6777 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 10 changed files with 112 additions and 261 deletions
hw/firmware_abi.h
  View file @513f789
1 1 #ifndef FIRMWARE_ABI_H
2 2 #define FIRMWARE_ABI_H
3 3  
4   -#ifndef __ASSEMBLY__
5   -/* Open Hack'Ware NVRAM configuration structure */
6   -
7   -/* Version 3 */
8   -typedef struct ohwcfg_v3_t ohwcfg_v3_t;
9   -struct ohwcfg_v3_t {
10   - /* 0x00: structure identifier */
11   - uint8_t struct_ident[0x10];
12   - /* 0x10: structure version and NVRAM description */
13   - uint32_t struct_version;
14   - uint16_t nvram_size;
15   - uint16_t pad0;
16   - uint16_t nvram_arch_ptr;
17   - uint16_t nvram_arch_size;
18   - uint16_t nvram_arch_crc;
19   - uint8_t pad1[0x02];
20   - /* 0x20: host architecture */
21   - uint8_t arch[0x10];
22   - /* 0x30: RAM/ROM description */
23   - uint64_t RAM0_base;
24   - uint64_t RAM0_size;
25   - uint64_t RAM1_base;
26   - uint64_t RAM1_size;
27   - uint64_t RAM2_base;
28   - uint64_t RAM2_size;
29   - uint64_t RAM3_base;
30   - uint64_t RAM3_size;
31   - uint64_t ROM_base;
32   - uint64_t ROM_size;
33   - /* 0x80: Kernel description */
34   - uint64_t kernel_image;
35   - uint64_t kernel_size;
36   - /* 0x90: Kernel command line */
37   - uint64_t cmdline;
38   - uint64_t cmdline_size;
39   - /* 0xA0: Kernel boot image */
40   - uint64_t initrd_image;
41   - uint64_t initrd_size;
42   - /* 0xB0: NVRAM image */
43   - uint64_t NVRAM_image;
44   - uint8_t pad2[8];
45   - /* 0xC0: graphic configuration */
46   - uint16_t width;
47   - uint16_t height;
48   - uint16_t depth;
49   - uint16_t graphic_flags;
50   - /* 0xC8: CPUs description */
51   - uint8_t nb_cpus;
52   - uint8_t boot_cpu;
53   - uint8_t nboot_devices;
54   - uint8_t pad3[5];
55   - /* 0xD0: boot devices */
56   - uint8_t boot_devices[0x10];
57   - /* 0xE0 */
58   - uint8_t pad4[0x1C]; /* 28 */
59   - /* 0xFC: checksum */
60   - uint16_t crc;
61   - uint8_t pad5[0x02];
62   -} __attribute__ (( packed ));
63   -
64   -#define OHW_GF_NOGRAPHICS 0x0001
65   -
66   -static inline uint16_t
67   -OHW_crc_update (uint16_t prev, uint16_t value)
68   -{
69   - uint16_t tmp;
70   - uint16_t pd, pd1, pd2;
71   -
72   - tmp = prev >> 8;
73   - pd = prev ^ value;
74   - pd1 = pd & 0x000F;
75   - pd2 = ((pd >> 4) & 0x000F) ^ pd1;
76   - tmp ^= (pd1 << 3) | (pd1 << 8);
77   - tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
78   -
79   - return tmp;
80   -}
81   -
82   -static inline uint16_t
83   -OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count)
84   -{
85   - uint32_t i;
86   - uint16_t crc = 0xFFFF;
87   - uint8_t *ptr = (uint8_t *)header;
88   - int odd;
89   -
90   - odd = count & 1;
91   - count &= ~1;
92   - for (i = 0; i != count; i++) {
93   - crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]);
94   - }
95   - if (odd) {
96   - crc = OHW_crc_update(crc, ptr[start + i] << 8);
97   - }
98   -
99   - return crc;
100   -}
101   -
102   -/* Sparc32 runtime NVRAM structure for SMP CPU boot */
103   -struct sparc_arch_cfg {
104   - uint32_t smp_ctx;
105   - uint32_t smp_ctxtbl;
106   - uint32_t smp_entry;
107   - uint8_t valid;
108   - uint8_t unused[51];
109   -};
110   -
111 4 /* OpenBIOS NVRAM partition */
112 5 struct OpenBIOS_nvpart_v1 {
113 6 uint8_t signature;
... ... @@ -175,24 +68,4 @@ Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id
175 68  
176 69 header->checksum = tmp;
177 70 }
178   -
179   -#else /* __ASSEMBLY__ */
180   -
181   -/* Structure offsets for asm use */
182   -
183   -/* Open Hack'Ware NVRAM configuration structure */
184   -#define OHW_ARCH_PTR 0x18
185   -#define OHW_RAM_SIZE 0x38
186   -#define OHW_BOOT_CPU 0xC9
187   -
188   -/* Sparc32 runtime NVRAM structure for SMP CPU boot */
189   -#define SPARC_SMP_CTX 0x0
190   -#define SPARC_SMP_CTXTBL 0x4
191   -#define SPARC_SMP_ENTRY 0x8
192   -#define SPARC_SMP_VALID 0xc
193   -
194   -/* Sun IDPROM structure at the end of NVRAM */
195   -#define SPARC_MACHINE_ID 0x1fd9
196   -
197   -#endif /* __ASSEMBLY__ */
198 71 #endif /* FIRMWARE_ABI_H */
... ...
hw/ppc_mac.h
  View file @513f789
... ... @@ -35,6 +35,7 @@
35 35 #define PROM_ADDR 0xfff00000
36 36  
37 37 #define KERNEL_LOAD_ADDR 0x01000000
  38 +#define CMDLINE_ADDR 0x017ff000
38 39 #define INITRD_LOAD_ADDR 0x01800000
39 40  
40 41 #define ESCC_CLOCK 3686400
... ...
hw/ppc_newworld.c
  View file @513f789
... ... @@ -78,6 +78,12 @@ static CPUReadMemoryFunc *unin_read[] = {
78 78 &unin_readl,
79 79 };
80 80  
  81 +static int fw_cfg_boot_set(void *opaque, const char *boot_device)
  82 +{
  83 + fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  84 + return 0;
  85 +}
  86 +
81 87 /* PowerPC Mac99 hardware initialisation */
82 88 static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
83 89 const char *boot_device,
... ... @@ -167,9 +173,24 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
167 173 }
168 174  
169 175 if (linux_boot) {
  176 + uint64_t lowaddr = 0;
170 177 kernel_base = KERNEL_LOAD_ADDR;
171   - /* now we can load the kernel */
172   - kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
  178 +
  179 + /* Now we can load the kernel. The first step tries to load the kernel
  180 + supposing PhysAddr = 0x00000000. If that was wrong the kernel is
  181 + loaded again, the new PhysAddr being computed from lowaddr. */
  182 + kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
  183 + if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
  184 + kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
  185 + NULL, 0, NULL);
  186 + }
  187 + if (kernel_size < 0)
  188 + kernel_size = load_aout(kernel_filename, kernel_base,
  189 + ram_size - kernel_base);
  190 + if (kernel_size < 0)
  191 + kernel_size = load_image_targphys(kernel_filename,
  192 + kernel_base,
  193 + ram_size - kernel_base);
173 194 if (kernel_size < 0) {
174 195 cpu_abort(env, "qemu: could not load kernel '%s'\n",
175 196 kernel_filename);
... ... @@ -321,6 +342,18 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
321 342 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
322 343 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
323 344 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_MAC99);
  345 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
  346 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
  347 + if (kernel_cmdline) {
  348 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
  349 + pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
  350 + } else {
  351 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
  352 + }
  353 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
  354 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
  355 + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
  356 + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
324 357 }
325 358  
326 359 QEMUMachine core99_machine = {
... ...
hw/ppc_oldworld.c
  View file @513f789
... ... @@ -108,6 +108,12 @@ static int vga_osi_call (CPUState *env)
108 108 return 1; /* osi_call handled */
109 109 }
110 110  
  111 +static int fw_cfg_boot_set(void *opaque, const char *boot_device)
  112 +{
  113 + fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  114 + return 0;
  115 +}
  116 +
111 117 static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
112 118 const char *boot_device,
113 119 const char *kernel_filename,
... ... @@ -118,8 +124,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
118 124 CPUState *env = NULL, *envs[MAX_CPUS];
119 125 char buf[1024];
120 126 qemu_irq *pic, **heathrow_irqs;
121   - nvram_t nvram;
122   - m48t59_t *m48t59;
123 127 int linux_boot, i;
124 128 ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
125 129 uint32_t kernel_base, initrd_base;
... ... @@ -129,7 +133,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
129 133 int vga_bios_size, bios_size;
130 134 int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
131 135 int escc_mem_index, ide_mem_index[2];
132   - int ppc_boot_device;
  136 + uint16_t ppc_boot_device;
133 137 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
134 138 int index;
135 139 void *fw_cfg;
... ... @@ -363,23 +367,24 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
363 367 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
364 368 graphic_depth = 15;
365 369  
366   - m48t59 = m48t59_init(0, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
367   - nvram.opaque = m48t59;
368   - nvram.read_fn = &m48t59_read;
369   - nvram.write_fn = &m48t59_write;
370   - PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
371   - ppc_boot_device, kernel_base, kernel_size,
372   - kernel_cmdline,
373   - initrd_base, initrd_size,
374   - /* XXX: need an option to load a NVRAM image */
375   - 0,
376   - graphic_width, graphic_height, graphic_depth);
377 370 /* No PCI init: the BIOS will do it */
378 371  
379 372 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
380 373 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
381 374 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
382 375 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
  376 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
  377 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
  378 + if (kernel_cmdline) {
  379 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
  380 + pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
  381 + } else {
  382 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
  383 + }
  384 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
  385 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
  386 + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
  387 + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
383 388 }
384 389  
385 390 QEMUMachine heathrow_machine = {
... ...
hw/sun4m.c
  View file @513f789
... ... @@ -174,24 +174,9 @@ void DMA_register_channel (int nchan,
174 174 {
175 175 }
176 176  
177   -static int nvram_boot_set(void *opaque, const char *boot_device)
  177 +static int fw_cfg_boot_set(void *opaque, const char *boot_device)
178 178 {
179   - unsigned int i;
180   - uint8_t image[sizeof(ohwcfg_v3_t)];
181   - ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
182   - m48t59_t *nvram = (m48t59_t *)opaque;
183   -
184   - for (i = 0; i < sizeof(image); i++)
185   - image[i] = m48t59_read(nvram, i) & 0xff;
186   -
187   - pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
188   - boot_device);
189   - header->nboot_devices = strlen(boot_device) & 0xff;
190   - header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
191   -
192   - for (i = 0; i < sizeof(image); i++)
193   - m48t59_write(nvram, i, image[i]);
194   -
  179 + fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
195 180 return 0;
196 181 }
197 182  
... ... @@ -204,48 +189,11 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
204 189 unsigned int i;
205 190 uint32_t start, end;
206 191 uint8_t image[0x1ff0];
207   - ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
208   - struct sparc_arch_cfg *sparc_header;
209 192 struct OpenBIOS_nvpart_v1 *part_header;
210 193  
211 194 memset(image, '\0', sizeof(image));
212 195  
213   - // Try to match PPC NVRAM
214   - pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
215   - "QEMU_BIOS");
216   - header->struct_version = cpu_to_be32(3); /* structure v3 */
217   -
218   - header->nvram_size = cpu_to_be16(0x2000);
219   - header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
220   - header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
221   - pstrcpy((char *)header->arch, sizeof(header->arch), arch);
222   - header->nb_cpus = smp_cpus & 0xff;
223   - header->RAM0_base = 0;
224   - header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
225   - pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
226   - boot_devices);
227   - header->nboot_devices = strlen(boot_devices) & 0xff;
228   - header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
229   - header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
230   - if (cmdline) {
231   - pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
232   - header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
233   - header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
234   - }
235   - // XXX add initrd_image, initrd_size
236   - header->width = cpu_to_be16(width);
237   - header->height = cpu_to_be16(height);
238   - header->depth = cpu_to_be16(depth);
239   - if (nographic)
240   - header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
241   -
242   - header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
243   -
244   - // Architecture specific header
245   - start = sizeof(ohwcfg_v3_t);
246   - sparc_header = (struct sparc_arch_cfg *)&image[start];
247   - sparc_header->valid = 0;
248   - start += sizeof(struct sparc_arch_cfg);
  196 + start = 0;
249 197  
250 198 // OpenBIOS nvram variables
251 199 // Variable partition
... ... @@ -277,8 +225,6 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
277 225  
278 226 for (i = 0; i < sizeof(image); i++)
279 227 m48t59_write(nvram, i, image[i]);
280   -
281   - qemu_register_boot_set(nvram_boot_set, nvram);
282 228 }
283 229  
284 230 static void *slavio_intctl;
... ... @@ -604,6 +550,18 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
604 550 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
605 551 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
606 552 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
  553 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
  554 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
  555 + if (kernel_cmdline) {
  556 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
  557 + pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
  558 + } else {
  559 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
  560 + }
  561 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
  562 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
  563 + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
  564 + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
607 565 }
608 566  
609 567 enum {
... ... @@ -1362,6 +1320,19 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1362 1320 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1363 1321 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1364 1322 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
  1323 + fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
  1324 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
  1325 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
  1326 + if (kernel_cmdline) {
  1327 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
  1328 + pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
  1329 + } else {
  1330 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
  1331 + }
  1332 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
  1333 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
  1334 + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
  1335 + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1365 1336 }
1366 1337  
1367 1338 /* SPARCserver 1000 hardware initialisation */
... ... @@ -1580,6 +1551,19 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1580 1551 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1581 1552 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1582 1553 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
  1554 + fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
  1555 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
  1556 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
  1557 + if (kernel_cmdline) {
  1558 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
  1559 + pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
  1560 + } else {
  1561 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
  1562 + }
  1563 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
  1564 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
  1565 + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
  1566 + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1583 1567 }
1584 1568  
1585 1569 /* SPARCstation 2 hardware initialisation */
... ...
hw/sun4u.c
  View file @513f789
... ... @@ -89,24 +89,9 @@ void DMA_register_channel (int nchan,
89 89 {
90 90 }
91 91  
92   -static int nvram_boot_set(void *opaque, const char *boot_device)
  92 +static int fw_cfg_boot_set(void *opaque, const char *boot_device)
93 93 {
94   - unsigned int i;
95   - uint8_t image[sizeof(ohwcfg_v3_t)];
96   - ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
97   - m48t59_t *nvram = (m48t59_t *)opaque;
98   -
99   - for (i = 0; i < sizeof(image); i++)
100   - image[i] = m48t59_read(nvram, i) & 0xff;
101   -
102   - pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
103   - boot_device);
104   - header->nboot_devices = strlen(boot_device) & 0xff;
105   - header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
106   -
107   - for (i = 0; i < sizeof(image); i++)
108   - m48t59_write(nvram, i, image[i]);
109   -
  94 + fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
110 95 return 0;
111 96 }
112 97  
... ... @@ -124,51 +109,11 @@ static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
124 109 unsigned int i;
125 110 uint32_t start, end;
126 111 uint8_t image[0x1ff0];
127   - ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
128   - struct sparc_arch_cfg *sparc_header;
129 112 struct OpenBIOS_nvpart_v1 *part_header;
130 113  
131 114 memset(image, '\0', sizeof(image));
132 115  
133   - // Try to match PPC NVRAM
134   - pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
135   - "QEMU_BIOS");
136   - header->struct_version = cpu_to_be32(3); /* structure v3 */
137   -
138   - header->nvram_size = cpu_to_be16(NVRAM_size);
139   - header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
140   - header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
141   - pstrcpy((char *)header->arch, sizeof(header->arch), arch);
142   - header->nb_cpus = smp_cpus & 0xff;
143   - header->RAM0_base = 0;
144   - header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
145   - pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
146   - boot_devices);
147   - header->nboot_devices = strlen(boot_devices) & 0xff;
148   - header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
149   - header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
150   - if (cmdline) {
151   - pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
152   - header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
153   - header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
154   - }
155   - header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
156   - header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
157   - header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
158   -
159   - header->width = cpu_to_be16(width);
160   - header->height = cpu_to_be16(height);
161   - header->depth = cpu_to_be16(depth);
162   - if (nographic)
163   - header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
164   -
165   - header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
166   -
167   - // Architecture specific header
168   - start = sizeof(ohwcfg_v3_t);
169   - sparc_header = (struct sparc_arch_cfg *)&image[start];
170   - sparc_header->valid = 0;
171   - start += sizeof(struct sparc_arch_cfg);
  116 + start = 0;
172 117  
173 118 // OpenBIOS nvram variables
174 119 // Variable partition
... ... @@ -200,8 +145,6 @@ static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
200 145 for (i = 0; i < sizeof(image); i++)
201 146 m48t59_write(nvram, i, image[i]);
202 147  
203   - qemu_register_boot_set(nvram_boot_set, nvram);
204   -
205 148 return 0;
206 149 }
207 150  
... ... @@ -575,6 +518,18 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
575 518 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
576 519 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
577 520 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
  521 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
  522 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
  523 + if (kernel_cmdline) {
  524 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
  525 + pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
  526 + } else {
  527 + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
  528 + }
  529 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
  530 + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
  531 + fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
  532 + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
578 533 }
579 534  
580 535 enum {
... ...
pc-bios/README
  View file @513f789
... ... @@ -42,7 +42,7 @@
42 42 firmware implementation. The goal is to implement a 100% IEEE
43 43 1275-1994 (referred to as Open Firmware) compliant firmware.
44 44 The included images for Sparc32, Sparc64 and PowerPC (for 32 and 64 bit
45   - PPC CPUs) are built from OpenBIOS 1.0 release (SVN revision 463).
  45 + PPC CPUs) are built from OpenBIOS SVN revision 479.
46 46  
47 47 - The PXE roms come from Rom-o-Matic etherboot 5.4.2.
48 48 pcnet32:pcnet32 -- [0x1022,0x2000]
... ...
pc-bios/openbios-ppc
View file @513f789
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pc-bios/openbios-sparc32
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pc-bios/openbios-sparc64
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