gwj / at91sam9263 · Commits

Commit 4efbe58fb57314f422578a543fe3f47ffc854b68

Authored by aurel32
1 parent f65ed4c1

MIPS Magnum: fix memory-mapped i8042 

Current implementation of memory-mapped i8042 controller is atm
implemented with an interface shift (it_shift) parameter, like most all
memory-mapped devices in Qemu.
However, this isn't suitable for MIPS Magnum, where i8042 controller is at
0x80005000 up to 0x80005fff.

Thomas Bogendoerfer (from #mipslinux) tested the behaviour of a real
machine, and found that odd addresses are for status/command register, and
even addresses for data register.

Attached patch implements this behaviour by replacing the it_shift
parameter by a mask one.
Incidentally, keyboard now works on OpenBSD 2.3, which accesses i8042
controller at 0x80005060 and 0x80005061.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5962 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 14 additions and 20 deletions
hw/mips_jazz.c
  View file @4efbe58
... ... @@ -229,7 +229,7 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
229 229 cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
230 230  
231 231 /* Keyboard (i8042) */
232   - i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0);
  232 + i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
233 233  
234 234 /* Serial ports */
235 235 if (serial_hds[0])
... ...
... ... @@ -71,7 +71,8 @@ void *vmmouse_init(void *m);
71 71  
72 72 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
73 73 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
74   - target_phys_addr_t base, int it_shift);
  74 + target_phys_addr_t base, ram_addr_t size,
  75 + target_phys_addr_t mask);
75 76  
76 77 /* mc146818rtc.c */
77 78  
... ...
hw/pckbd.c
  View file @4efbe58
... ... @@ -125,7 +125,7 @@ typedef struct KBDState {
125 125  
126 126 qemu_irq irq_kbd;
127 127 qemu_irq irq_mouse;
128   - int it_shift;
  128 + target_phys_addr_t mask;
129 129 } KBDState;
130 130  
131 131 static KBDState kbd_state;
... ... @@ -391,28 +391,20 @@ static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
391 391 {
392 392 KBDState *s = opaque;
393 393  
394   - switch (addr >> s->it_shift) {
395   - case 0:
396   - return kbd_read_data(s, 0) & 0xff;
397   - case 1:
  394 + if (addr & s->mask)
398 395 return kbd_read_status(s, 0) & 0xff;
399   - default:
400   - return 0xff;
401   - }
  396 + else
  397 + return kbd_read_data(s, 0) & 0xff;
402 398 }
403 399  
404 400 static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
405 401 {
406 402 KBDState *s = opaque;
407 403  
408   - switch (addr >> s->it_shift) {
409   - case 0:
410   - kbd_write_data(s, 0, value & 0xff);
411   - break;
412   - case 1:
  404 + if (addr & s->mask)
413 405 kbd_write_command(s, 0, value & 0xff);
414   - break;
415   - }
  406 + else
  407 + kbd_write_data(s, 0, value & 0xff);
416 408 }
417 409  
418 410 static CPUReadMemoryFunc *kbd_mm_read[] = {
... ... @@ -428,19 +420,20 @@ static CPUWriteMemoryFunc *kbd_mm_write[] = {
428 420 };
429 421  
430 422 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
431   - target_phys_addr_t base, int it_shift)
  423 + target_phys_addr_t base, ram_addr_t size,
  424 + target_phys_addr_t mask)
432 425 {
433 426 KBDState *s = &kbd_state;
434 427 int s_io_memory;
435 428  
436 429 s->irq_kbd = kbd_irq;
437 430 s->irq_mouse = mouse_irq;
438   - s->it_shift = it_shift;
  431 + s->mask = mask;
439 432  
440 433 kbd_reset(s);
441 434 register_savevm("pckbd", 0, 3, kbd_save, kbd_load, s);
442 435 s_io_memory = cpu_register_io_memory(0, kbd_mm_read, kbd_mm_write, s);
443   - cpu_register_physical_memory(base, 2 << it_shift, s_io_memory);
  436 + cpu_register_physical_memory(base, size, s_io_memory);
444 437  
445 438 s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
446 439 s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
... ...