disable debug, use common nand code in emulation,

we reach mount root stage, though read seems failed

disable debug, use common nand code in emulation,
we reach mount root stage, though read seems failed
Evgeniy Dushistov
1 parent 66cbdd2f
Showing 5 changed files with 36 additions and 33 deletions
hw/at91.h
hw/at91_nand.c
hw/at91_pdc.c
hw/at91sam9.c
hw/nand.c
@@ -56,6 +56,7 @@ extern void at91_pdc_reset(PDCState *s);
 extern void at91_pdc_write(void *opaque, target_phys_addr_t offset, uint32_t val);
 extern uint32_t at91_pdc_read(void *opaque, target_phys_addr_t offset);
-extern void at91_nand_register(void);
+struct NANDFlashState;
+extern void at91_nand_register(struct NANDFlashState *st);
 #endif /* !AT91_H */
 #include <stdio.h>
 #include "hw.h"
+#include "flash.h"
 #include "at91.h"
 typedef struct NandState {
-    unsigned int cmd;
+    NANDFlashState *nand_state;
 } NandState;
-#define AT91_NAND_DEBUG
+//#define AT91_NAND_DEBUG
 #ifdef AT91_NAND_DEBUG
 #define DPRINTF(fmt, ...)                           \
     do {                                            \
@@ -23,23 +24,19 @@ static uint32_t at91_nand_mem_read(void *opaque, target_phys_addr_t offset)
 {
     NandState *s = opaque;
-    DPRINTF("(IP %X) read from %X\n", g_env->regs[15], offset);
-    switch (s->cmd) {
-    case 0x70:
-        s->cmd = 0;
-        return 0x40;
-    default:
-        return 0x0;
-    }
+    uint8_t res = nand_getio(s->nand_state);
+    DPRINTF("(IP %X) read from %X (res %X)\n", g_env->regs[15], offset, res);
+    return res;
 }
 static void at91_nand_mem_write(void *opaque, target_phys_addr_t offset,
                 uint32_t value)
 {
-    NandState *s = opaque;
+    NandState *s = opaque;        
+    nand_setpins(s->nand_state, offset & (1 << 22), offset & (1 << 21), 0, 1, 0);
     DPRINTF("(IP %X) write to %X %X\n", g_env->regs[15], offset, value);
-    s->cmd = value;
+    nand_setio(s->nand_state, value & 0xFF);
 }
 static CPUReadMemoryFunc *at91_nand_readfn[] = {
@@ -54,12 +51,13 @@ static CPUWriteMemoryFunc *at91_nand_writefn[] = {
     at91_nand_mem_write,
 };
-void at91_nand_register(void)
+void at91_nand_register(NANDFlashState *st)
 {
     NandState *s;
     int iomemtype;
     s = qemu_mallocz(sizeof(*s));
+    s->nand_state = st;
     iomemtype = cpu_register_io_memory(at91_nand_readfn, at91_nand_writefn, s);
     cpu_register_physical_memory(0x40000000, 0x10000000, iomemtype);
 }
@@ -24,7 +24,7 @@
 #define PDC_PTCR_TXTEN  (1 << 8)
 #define PDC_PTCR_TXTDIS (1 << 9)
-#define AT91_PDC_DEBUG
+//#define AT91_PDC_DEBUG
 #ifdef AT91_PDC_DEBUG
 #define DPRINTF(fmt, ...)                           \
     do {                                            \
@@ -344,6 +344,8 @@ static void at91sam9_init(ram_addr_t ram_size,
     dinfo = drive_get(IF_PFLASH, 0, 0);
     if (dinfo) {
         if (bms) {
+            NANDFlashState *nand_state;
+
             if (spi_flash_register(dinfo->bdrv, 4 * 1024 * 1024, cs0_spi_handler) < 0) {
                 fprintf(stderr, "init of spi flash failed\n");
                 exit(EXIT_FAILURE);
@@ -352,7 +354,8 @@ static void at91sam9_init(ram_addr_t ram_size,
             //rom
             cpu_register_physical_memory(0x0, 100 * 1024,
                                          sam9->bootrom | IO_MEM_ROMD);
-            at91_nand_register();
+            nand_state = nand_init(NAND_MFR_MICRON, 0xba);
+            at91_nand_register(nand_state);
         } else {
             //nor flash
             ram_addr_t nor_flash_mem = qemu_ram_alloc(NOR_FLASH_SIZE);
@@ -39,7 +39,7 @@
 # define NAND_IOSTATUS_PLANE1	(1 << 2)
 # define NAND_IOSTATUS_PLANE2	(1 << 3)
 # define NAND_IOSTATUS_PLANE3	(1 << 4)
-# define NAND_IOSTATUS_BUSY	(1 << 6)
+# define NAND_IOSTATUS_READY	(1 << 6)
 # define NAND_IOSTATUS_UNPROTCT	(1 << 7)
 # define MAX_PAGE		0x800
@@ -207,7 +207,8 @@ static void nand_reset(NANDFlashState *s)
     s->addrlen = 0;
     s->iolen = 0;
     s->offset = 0;
-    s->status &= NAND_IOSTATUS_UNPROTCT;
+    s->status = NAND_IOSTATUS_READY;
+    s->status &= ~NAND_IOSTATUS_UNPROTCT;
 }
 static void nand_command(NANDFlashState *s)
@@ -358,11 +359,11 @@ void nand_setio(NANDFlashState *s, uint8_t value)
         }
         if (value == NAND_CMD_READ0)
             s->offset = 0;
-	else if (value == NAND_CMD_READ1) {
+        else if (value == NAND_CMD_READ1) {
             s->offset = 0x100;
             value = NAND_CMD_READ0;
         }
-	else if (value == NAND_CMD_READ2) {
+        else if (value == NAND_CMD_READ2) {
             s->offset = 1 << s->page_shift;
             value = NAND_CMD_READ0;
         }
@@ -370,12 +371,12 @@ void nand_setio(NANDFlashState *s, uint8_t value)
         s->cmd = value;
         if (s->cmd == NAND_CMD_READSTATUS ||
-                s->cmd == NAND_CMD_PAGEPROGRAM2 ||
-                s->cmd == NAND_CMD_BLOCKERASE1 ||
-                s->cmd == NAND_CMD_BLOCKERASE2 ||
-                s->cmd == NAND_CMD_NOSERIALREAD2 ||
-                s->cmd == NAND_CMD_RANDOMREAD2 ||
-                s->cmd == NAND_CMD_RESET)
+            s->cmd == NAND_CMD_PAGEPROGRAM2 ||
+            s->cmd == NAND_CMD_BLOCKERASE1 ||
+            s->cmd == NAND_CMD_BLOCKERASE2 ||
+            s->cmd == NAND_CMD_NOSERIALREAD2 ||
+            s->cmd == NAND_CMD_RANDOMREAD2 ||
+            s->cmd == NAND_CMD_RESET)
             nand_command(s);
         if (s->cmd != NAND_CMD_RANDOMREAD2) {
@@ -392,14 +393,14 @@ void nand_setio(NANDFlashState *s, uint8_t value)
             nand_command(s);
         if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
-                s->addrlen == 3 && (
-                    s->cmd == NAND_CMD_READ0 ||
-                    s->cmd == NAND_CMD_PAGEPROGRAM1))
+            s->addrlen == 3 && (
+                s->cmd == NAND_CMD_READ0 ||
+                s->cmd == NAND_CMD_PAGEPROGRAM1))
             nand_command(s);
         if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
-               s->addrlen == 4 && (
-                    s->cmd == NAND_CMD_READ0 ||
-                    s->cmd == NAND_CMD_PAGEPROGRAM1))
+            s->addrlen == 4 && (
+                s->cmd == NAND_CMD_READ0 ||
+                s->cmd == NAND_CMD_PAGEPROGRAM1))
             nand_command(s);
     }
@@ -408,7 +409,7 @@ void nand_setio(NANDFlashState *s, uint8_t value)
             s->io[s->iolen ++] = value;
     } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
         if ((s->addr & ((1 << s->addr_shift) - 1)) <
-                (1 << s->page_shift) + (1 << s->oob_shift)) {
+            (1 << s->page_shift) + (1 << s->oob_shift)) {
             s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] = value;
             s->addr ++;
         }