gwj / at91sam9263 · Commits

Commit 4e7774427dcc596225dbb6dc720a4bf637aba8d8

Authored by j_mayer
1 parent 8ccc2ace

Fix PowerPC 74xx definitions. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 228 additions and 49 deletions
target-ppc/cpu.h
  View file @4e77744
... ... @@ -1235,7 +1235,7 @@ static inline int cpu_mmu_index (CPUState *env)
1235 1235 #define SPR_40x_EVPR (0x3D6)
1236 1236 #define SPR_L3PM (0x3D7)
1237 1237 #define SPR_403_CDBCR (0x3D7)
1238   -#define SPR_L3OHCR (0x3D8)
  1238 +#define SPR_L3ITCR0 (0x3D8)
1239 1239 #define SPR_TCR (0x3D8)
1240 1240 #define SPR_40x_TSR (0x3D8)
1241 1241 #define SPR_IBR (0x3DA)
... ... @@ -1248,7 +1248,7 @@ static inline int cpu_mmu_index (CPUState *env)
1248 1248 #define SPR_40x_SRR2 (0x3DE)
1249 1249 #define SPR_SER (0x3DF)
1250 1250 #define SPR_40x_SRR3 (0x3DF)
1251   -#define SPR_L3ITCR0 (0x3E8)
  1251 +#define SPR_L3OHCR (0x3E8)
1252 1252 #define SPR_L3ITCR1 (0x3E9)
1253 1253 #define SPR_L3ITCR2 (0x3EA)
1254 1254 #define SPR_L3ITCR3 (0x3EB)
... ... @@ -1277,6 +1277,7 @@ static inline int cpu_mmu_index (CPUState *env)
1277 1277 #define SPR_MSSCR0 (0x3F6)
1278 1278 #define SPR_970_HID5 (0x3F6)
1279 1279 #define SPR_MSSSR0 (0x3F7)
  1280 +#define SPR_MSSCR1 (0x3F7)
1280 1281 #define SPR_DABRX (0x3F7)
1281 1282 #define SPR_40x_DAC2 (0x3F7)
1282 1283 #define SPR_MMUCFG (0x3F7)
... ...
target-ppc/translate_init.c
  View file @4e77744
... ... @@ -1149,11 +1149,6 @@ static void gen_spr_74xx (CPUPPCState *env)
1149 1149 &spr_read_generic, &spr_write_generic,
1150 1150 0x00000000);
1151 1151 /* XXX : not implemented */
1152   - spr_register(env, SPR_UBAMR, "UBAMR",
1153   - &spr_read_ureg, SPR_NOACCESS,
1154   - &spr_read_ureg, SPR_NOACCESS,
1155   - 0x00000000);
1156   - /* XXX : not implemented */
1157 1152 spr_register(env, SPR_MSSCR0, "MSSCR0",
1158 1153 SPR_NOACCESS, SPR_NOACCESS,
1159 1154 &spr_read_generic, &spr_write_generic,
... ... @@ -1195,30 +1190,6 @@ static void gen_l3_ctrl (CPUPPCState *env)
1195 1190 SPR_NOACCESS, SPR_NOACCESS,
1196 1191 &spr_read_generic, &spr_write_generic,
1197 1192 0x00000000);
1198   - /* L3ITCR1 */
1199   - /* XXX : not implemented */
1200   - spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1201   - SPR_NOACCESS, SPR_NOACCESS,
1202   - &spr_read_generic, &spr_write_generic,
1203   - 0x00000000);
1204   - /* L3ITCR2 */
1205   - /* XXX : not implemented */
1206   - spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1207   - SPR_NOACCESS, SPR_NOACCESS,
1208   - &spr_read_generic, &spr_write_generic,
1209   - 0x00000000);
1210   - /* L3ITCR3 */
1211   - /* XXX : not implemented */
1212   - spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1213   - SPR_NOACCESS, SPR_NOACCESS,
1214   - &spr_read_generic, &spr_write_generic,
1215   - 0x00000000);
1216   - /* L3OHCR */
1217   - /* XXX : not implemented */
1218   - spr_register(env, SPR_L3OHCR, "L3OHCR",
1219   - SPR_NOACCESS, SPR_NOACCESS,
1220   - &spr_read_generic, &spr_write_generic,
1221   - 0x00000000);
1222 1193 /* L3PM */
1223 1194 /* XXX : not implemented */
1224 1195 spr_register(env, SPR_L3PM, "L3PM",
... ... @@ -3052,6 +3023,14 @@ static int check_pow_hid0 (CPUPPCState *env)
3052 3023 return 0;
3053 3024 }
3054 3025  
  3026 +static int check_pow_hid0_74xx (CPUPPCState *env)
  3027 +{
  3028 + if (env->spr[SPR_HID0] & 0x00600000)
  3029 + return 1;
  3030 +
  3031 + return 0;
  3032 +}
  3033 +
3055 3034 /*****************************************************************************/
3056 3035 /* PowerPC implementations definitions */
3057 3036  
... ... @@ -4829,6 +4808,7 @@ static void init_proc_750cl (CPUPPCState *env)
4829 4808 ppc6xx_irq_init(env);
4830 4809 }
4831 4810  
  4811 +/* PowerPC 750CX */
4832 4812 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4833 4813 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4834 4814 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
... ... @@ -4876,9 +4856,8 @@ static void init_proc_750cx (CPUPPCState *env)
4876 4856 0x00000000);
4877 4857 /* Memory management */
4878 4858 gen_low_BATs(env);
4879   - /* XXX: high BATs are also present but are known to be bugged on
4880   - * die version 1.x
4881   - */
  4859 + /* PowerPC 750cx has 8 DBATs and 8 IBATs */
  4860 + gen_high_BATs(env);
4882 4861 init_excp_750cx(env);
4883 4862 env->dcache_line_size = 32;
4884 4863 env->icache_line_size = 32;
... ... @@ -5147,7 +5126,7 @@ static void init_proc_755 (CPUPPCState *env)
5147 5126 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5148 5127 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5149 5128 POWERPC_FLAG_BUS_CLK)
5150   -#define check_pow_7400 check_pow_hid0
  5129 +#define check_pow_7400 check_pow_hid0_74xx
5151 5130  
5152 5131 static void init_proc_7400 (CPUPPCState *env)
5153 5132 {
... ... @@ -5157,6 +5136,17 @@ static void init_proc_7400 (CPUPPCState *env)
5157 5136 gen_tbl(env);
5158 5137 /* 74xx specific SPR */
5159 5138 gen_spr_74xx(env);
  5139 + /* XXX : not implemented */
  5140 + spr_register(env, SPR_UBAMR, "UBAMR",
  5141 + &spr_read_ureg, SPR_NOACCESS,
  5142 + &spr_read_ureg, SPR_NOACCESS,
  5143 + 0x00000000);
  5144 + /* XXX: this seems not implemented on all revisions. */
  5145 + /* XXX : not implemented */
  5146 + spr_register(env, SPR_MSSCR1, "MSSCR1",
  5147 + SPR_NOACCESS, SPR_NOACCESS,
  5148 + &spr_read_generic, &spr_write_generic,
  5149 + 0x00000000);
5160 5150 /* Thermal management */
5161 5151 gen_spr_thrm(env);
5162 5152 /* Memory management */
... ... @@ -5188,7 +5178,7 @@ static void init_proc_7400 (CPUPPCState *env)
5188 5178 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5189 5179 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5190 5180 POWERPC_FLAG_BUS_CLK)
5191   -#define check_pow_7410 check_pow_hid0
  5181 +#define check_pow_7410 check_pow_hid0_74xx
5192 5182  
5193 5183 static void init_proc_7410 (CPUPPCState *env)
5194 5184 {
... ... @@ -5198,6 +5188,11 @@ static void init_proc_7410 (CPUPPCState *env)
5198 5188 gen_tbl(env);
5199 5189 /* 74xx specific SPR */
5200 5190 gen_spr_74xx(env);
  5191 + /* XXX : not implemented */
  5192 + spr_register(env, SPR_UBAMR, "UBAMR",
  5193 + &spr_read_ureg, SPR_NOACCESS,
  5194 + &spr_read_ureg, SPR_NOACCESS,
  5195 + 0x00000000);
5201 5196 /* Thermal management */
5202 5197 gen_spr_thrm(env);
5203 5198 /* L2PMCR */
... ... @@ -5241,7 +5236,7 @@ static void init_proc_7410 (CPUPPCState *env)
5241 5236 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5242 5237 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5243 5238 POWERPC_FLAG_BUS_CLK)
5244   -#define check_pow_7440 check_pow_hid0
  5239 +#define check_pow_7440 check_pow_hid0_74xx
5245 5240  
5246 5241 __attribute__ (( unused ))
5247 5242 static void init_proc_7440 (CPUPPCState *env)
... ... @@ -5252,6 +5247,11 @@ static void init_proc_7440 (CPUPPCState *env)
5252 5247 gen_tbl(env);
5253 5248 /* 74xx specific SPR */
5254 5249 gen_spr_74xx(env);
  5250 + /* XXX : not implemented */
  5251 + spr_register(env, SPR_UBAMR, "UBAMR",
  5252 + &spr_read_ureg, SPR_NOACCESS,
  5253 + &spr_read_ureg, SPR_NOACCESS,
  5254 + 0x00000000);
5255 5255 /* LDSTCR */
5256 5256 /* XXX : not implemented */
5257 5257 spr_register(env, SPR_LDSTCR, "LDSTCR",
... ... @@ -5321,7 +5321,7 @@ static void init_proc_7440 (CPUPPCState *env)
5321 5321 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5322 5322 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5323 5323 POWERPC_FLAG_BUS_CLK)
5324   -#define check_pow_7450 check_pow_hid0
  5324 +#define check_pow_7450 check_pow_hid0_74xx
5325 5325  
5326 5326 __attribute__ (( unused ))
5327 5327 static void init_proc_7450 (CPUPPCState *env)
... ... @@ -5334,6 +5334,35 @@ static void init_proc_7450 (CPUPPCState *env)
5334 5334 gen_spr_74xx(env);
5335 5335 /* Level 3 cache control */
5336 5336 gen_l3_ctrl(env);
  5337 + /* L3ITCR1 */
  5338 + /* XXX : not implemented */
  5339 + spr_register(env, SPR_L3ITCR1, "L3ITCR1",
  5340 + SPR_NOACCESS, SPR_NOACCESS,
  5341 + &spr_read_generic, &spr_write_generic,
  5342 + 0x00000000);
  5343 + /* L3ITCR2 */
  5344 + /* XXX : not implemented */
  5345 + spr_register(env, SPR_L3ITCR2, "L3ITCR2",
  5346 + SPR_NOACCESS, SPR_NOACCESS,
  5347 + &spr_read_generic, &spr_write_generic,
  5348 + 0x00000000);
  5349 + /* L3ITCR3 */
  5350 + /* XXX : not implemented */
  5351 + spr_register(env, SPR_L3ITCR3, "L3ITCR3",
  5352 + SPR_NOACCESS, SPR_NOACCESS,
  5353 + &spr_read_generic, &spr_write_generic,
  5354 + 0x00000000);
  5355 + /* L3OHCR */
  5356 + /* XXX : not implemented */
  5357 + spr_register(env, SPR_L3OHCR, "L3OHCR",
  5358 + SPR_NOACCESS, SPR_NOACCESS,
  5359 + &spr_read_generic, &spr_write_generic,
  5360 + 0x00000000);
  5361 + /* XXX : not implemented */
  5362 + spr_register(env, SPR_UBAMR, "UBAMR",
  5363 + &spr_read_ureg, SPR_NOACCESS,
  5364 + &spr_read_ureg, SPR_NOACCESS,
  5365 + 0x00000000);
5337 5366 /* LDSTCR */
5338 5367 /* XXX : not implemented */
5339 5368 spr_register(env, SPR_LDSTCR, "LDSTCR",
... ... @@ -5403,7 +5432,7 @@ static void init_proc_7450 (CPUPPCState *env)
5403 5432 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5404 5433 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5405 5434 POWERPC_FLAG_BUS_CLK)
5406   -#define check_pow_7445 check_pow_hid0
  5435 +#define check_pow_7445 check_pow_hid0_74xx
5407 5436  
5408 5437 __attribute__ (( unused ))
5409 5438 static void init_proc_7445 (CPUPPCState *env)
... ... @@ -5517,7 +5546,7 @@ static void init_proc_7445 (CPUPPCState *env)
5517 5546 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5518 5547 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5519 5548 POWERPC_FLAG_BUS_CLK)
5520   -#define check_pow_7455 check_pow_hid0
  5549 +#define check_pow_7455 check_pow_hid0_74xx
5521 5550  
5522 5551 __attribute__ (( unused ))
5523 5552 static void init_proc_7455 (CPUPPCState *env)
... ... @@ -5613,6 +5642,146 @@ static void init_proc_7455 (CPUPPCState *env)
5613 5642 ppc6xx_irq_init(env);
5614 5643 }
5615 5644  
  5645 +/* PowerPC 7457 (aka G4) */
  5646 +#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
  5647 + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
  5648 + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
  5649 + PPC_FLOAT_STFIWX | \
  5650 + PPC_CACHE | PPC_CACHE_ICBI | \
  5651 + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
  5652 + PPC_MEM_SYNC | PPC_MEM_EIEIO | \
  5653 + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
  5654 + PPC_MEM_TLBIA | PPC_74xx_TLB | \
  5655 + PPC_SEGMENT | PPC_EXTERN | \
  5656 + PPC_ALTIVEC)
  5657 +#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
  5658 +#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
  5659 +#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
  5660 +#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
  5661 +#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
  5662 +#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
  5663 + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
  5664 + POWERPC_FLAG_BUS_CLK)
  5665 +#define check_pow_7457 check_pow_hid0_74xx
  5666 +
  5667 +__attribute__ (( unused ))
  5668 +static void init_proc_7457 (CPUPPCState *env)
  5669 +{
  5670 + gen_spr_ne_601(env);
  5671 + gen_spr_7xx(env);
  5672 + /* Time base */
  5673 + gen_tbl(env);
  5674 + /* 74xx specific SPR */
  5675 + gen_spr_74xx(env);
  5676 + /* Level 3 cache control */
  5677 + gen_l3_ctrl(env);
  5678 + /* L3ITCR1 */
  5679 + /* XXX : not implemented */
  5680 + spr_register(env, SPR_L3ITCR1, "L3ITCR1",
  5681 + SPR_NOACCESS, SPR_NOACCESS,
  5682 + &spr_read_generic, &spr_write_generic,
  5683 + 0x00000000);
  5684 + /* L3ITCR2 */
  5685 + /* XXX : not implemented */
  5686 + spr_register(env, SPR_L3ITCR2, "L3ITCR2",
  5687 + SPR_NOACCESS, SPR_NOACCESS,
  5688 + &spr_read_generic, &spr_write_generic,
  5689 + 0x00000000);
  5690 + /* L3ITCR3 */
  5691 + /* XXX : not implemented */
  5692 + spr_register(env, SPR_L3ITCR3, "L3ITCR3",
  5693 + SPR_NOACCESS, SPR_NOACCESS,
  5694 + &spr_read_generic, &spr_write_generic,
  5695 + 0x00000000);
  5696 + /* L3OHCR */
  5697 + /* XXX : not implemented */
  5698 + spr_register(env, SPR_L3OHCR, "L3OHCR",
  5699 + SPR_NOACCESS, SPR_NOACCESS,
  5700 + &spr_read_generic, &spr_write_generic,
  5701 + 0x00000000);
  5702 + /* LDSTCR */
  5703 + /* XXX : not implemented */
  5704 + spr_register(env, SPR_LDSTCR, "LDSTCR",
  5705 + SPR_NOACCESS, SPR_NOACCESS,
  5706 + &spr_read_generic, &spr_write_generic,
  5707 + 0x00000000);
  5708 + /* ICTRL */
  5709 + /* XXX : not implemented */
  5710 + spr_register(env, SPR_ICTRL, "ICTRL",
  5711 + SPR_NOACCESS, SPR_NOACCESS,
  5712 + &spr_read_generic, &spr_write_generic,
  5713 + 0x00000000);
  5714 + /* MSSSR0 */
  5715 + /* XXX : not implemented */
  5716 + spr_register(env, SPR_MSSSR0, "MSSSR0",
  5717 + SPR_NOACCESS, SPR_NOACCESS,
  5718 + &spr_read_generic, &spr_write_generic,
  5719 + 0x00000000);
  5720 + /* PMC */
  5721 + /* XXX : not implemented */
  5722 + spr_register(env, SPR_PMC5, "PMC5",
  5723 + SPR_NOACCESS, SPR_NOACCESS,
  5724 + &spr_read_generic, &spr_write_generic,
  5725 + 0x00000000);
  5726 + /* XXX : not implemented */
  5727 + spr_register(env, SPR_UPMC5, "UPMC5",
  5728 + &spr_read_ureg, SPR_NOACCESS,
  5729 + &spr_read_ureg, SPR_NOACCESS,
  5730 + 0x00000000);
  5731 + /* XXX : not implemented */
  5732 + spr_register(env, SPR_PMC6, "PMC6",
  5733 + SPR_NOACCESS, SPR_NOACCESS,
  5734 + &spr_read_generic, &spr_write_generic,
  5735 + 0x00000000);
  5736 + /* XXX : not implemented */
  5737 + spr_register(env, SPR_UPMC6, "UPMC6",
  5738 + &spr_read_ureg, SPR_NOACCESS,
  5739 + &spr_read_ureg, SPR_NOACCESS,
  5740 + 0x00000000);
  5741 + /* SPRGs */
  5742 + spr_register(env, SPR_SPRG4, "SPRG4",
  5743 + SPR_NOACCESS, SPR_NOACCESS,
  5744 + &spr_read_generic, &spr_write_generic,
  5745 + 0x00000000);
  5746 + spr_register(env, SPR_USPRG4, "USPRG4",
  5747 + &spr_read_ureg, SPR_NOACCESS,
  5748 + &spr_read_ureg, SPR_NOACCESS,
  5749 + 0x00000000);
  5750 + spr_register(env, SPR_SPRG5, "SPRG5",
  5751 + SPR_NOACCESS, SPR_NOACCESS,
  5752 + &spr_read_generic, &spr_write_generic,
  5753 + 0x00000000);
  5754 + spr_register(env, SPR_USPRG5, "USPRG5",
  5755 + &spr_read_ureg, SPR_NOACCESS,
  5756 + &spr_read_ureg, SPR_NOACCESS,
  5757 + 0x00000000);
  5758 + spr_register(env, SPR_SPRG6, "SPRG6",
  5759 + SPR_NOACCESS, SPR_NOACCESS,
  5760 + &spr_read_generic, &spr_write_generic,
  5761 + 0x00000000);
  5762 + spr_register(env, SPR_USPRG6, "USPRG6",
  5763 + &spr_read_ureg, SPR_NOACCESS,
  5764 + &spr_read_ureg, SPR_NOACCESS,
  5765 + 0x00000000);
  5766 + spr_register(env, SPR_SPRG7, "SPRG7",
  5767 + SPR_NOACCESS, SPR_NOACCESS,
  5768 + &spr_read_generic, &spr_write_generic,
  5769 + 0x00000000);
  5770 + spr_register(env, SPR_USPRG7, "USPRG7",
  5771 + &spr_read_ureg, SPR_NOACCESS,
  5772 + &spr_read_ureg, SPR_NOACCESS,
  5773 + 0x00000000);
  5774 + /* Memory management */
  5775 + gen_low_BATs(env);
  5776 + gen_high_BATs(env);
  5777 + gen_74xx_soft_tlb(env, 128, 2);
  5778 + init_excp_7450(env);
  5779 + env->dcache_line_size = 32;
  5780 + env->icache_line_size = 32;
  5781 + /* Allocate hardware IRQ controller */
  5782 + ppc6xx_irq_init(env);
  5783 +}
  5784 +
5616 5785 #if defined (TARGET_PPC64)
5617 5786 /* PowerPC 970 */
5618 5787 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
... ... @@ -6651,6 +6820,7 @@ enum {
6651 6820 CPU_POWERPC_7400_v10 = 0x000C0100,
6652 6821 CPU_POWERPC_7400_v11 = 0x000C0101,
6653 6822 CPU_POWERPC_7400_v20 = 0x000C0200,
  6823 + CPU_POWERPC_7400_v21 = 0x000C0201,
6654 6824 CPU_POWERPC_7400_v22 = 0x000C0202,
6655 6825 CPU_POWERPC_7400_v26 = 0x000C0206,
6656 6826 CPU_POWERPC_7400_v27 = 0x000C0207,
... ... @@ -6671,10 +6841,12 @@ enum {
6671 6841 CPU_POWERPC_7450_v10 = 0x80000100,
6672 6842 CPU_POWERPC_7450_v11 = 0x80000101,
6673 6843 CPU_POWERPC_7450_v12 = 0x80000102,
6674   - CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
  6844 + CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
6675 6845 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
6676   - CPU_POWERPC_74x1 = 0x80000203,
6677   - CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
  6846 +#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
  6847 + CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
  6848 + /* XXX: this entry might be a bug in some documentation */
  6849 + CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
6678 6850 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6679 6851 CPU_POWERPC_74x5_v10 = 0x80010100,
6680 6852 /* XXX: missing 0x80010200 */
... ... @@ -8300,6 +8472,8 @@ static const ppc_def_t ppc_defs[] = {
8300 8472 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8301 8473 /* PowerPC 7400 v2.0 (G4) */
8302 8474 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
  8475 + /* PowerPC 7400 v2.1 (G4) */
  8476 + POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
8303 8477 /* PowerPC 7400 v2.2 (G4) */
8304 8478 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
8305 8479 /* PowerPC 7400 v2.6 (G4) */
... ... @@ -8352,10 +8526,16 @@ static const ppc_def_t ppc_defs[] = {
8352 8526 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
8353 8527 /* PowerPC 7451 (G4) */
8354 8528 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
8355   - /* PowerPC 7441g (G4) */
8356   - POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
8357   - /* PowerPC 7451g (G4) */
8358   - POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
  8529 + /* PowerPC 7441 v2.1 (G4) */
  8530 + POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
  8531 + /* PowerPC 7441 v2.3 (G4) */
  8532 + POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
  8533 + /* PowerPC 7451 v2.3 (G4) */
  8534 + POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
  8535 + /* PowerPC 7441 v2.10 (G4) */
  8536 + POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
  8537 + /* PowerPC 7451 v2.10 (G4) */
  8538 + POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
8359 8539 /* PowerPC 7445 (G4) */
8360 8540 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
8361 8541 /* PowerPC 7455 (G4) */
... ... @@ -8396,8 +8576,6 @@ static const ppc_def_t ppc_defs[] = {
8396 8576 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
8397 8577 /* PowerPC 7457 v1.1 (G4) */
8398 8578 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
8399   - /* PowerPC 7447 v1.2 (G4) */
8400   - POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
8401 8579 /* PowerPC 7457 v1.2 (G4) */
8402 8580 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
8403 8581 /* PowerPC 7447A (G4) */
... ...