gwj / at91sam9263 · Commits

Commit 4e290a0b714650097f10f9bfb06ab1ef6173afc1

Authored by j_mayer
1 parent 3391c818

Share input pins and internal interrupt controller between all PowerPC 40x. 

Fix critical input interrupt generation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3299 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 41 additions and 39 deletions
hw/ppc.c
  View file @4e290a0
... ... @@ -284,8 +284,8 @@ void ppc970_irq_init (CPUState *env)
284 284 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
285 285 }
286 286  
287   -/* PowerPC 405 internal IRQ controller */
288   -static void ppc405_set_irq (void *opaque, int pin, int level)
  287 +/* PowerPC 40x internal IRQ controller */
  288 +static void ppc40x_set_irq (void *opaque, int pin, int level)
289 289 {
290 290 CPUState *env = opaque;
291 291 int cur_level;
... ... @@ -300,7 +300,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
300 300 /* Don't generate spurious events */
301 301 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
302 302 switch (pin) {
303   - case PPC405_INPUT_RESET_SYS:
  303 + case PPC40x_INPUT_RESET_SYS:
304 304 if (level) {
305 305 #if defined(PPC_DEBUG_IRQ)
306 306 if (loglevel & CPU_LOG_INT) {
... ... @@ -311,7 +311,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
311 311 ppc40x_system_reset(env);
312 312 }
313 313 break;
314   - case PPC405_INPUT_RESET_CHIP:
  314 + case PPC40x_INPUT_RESET_CHIP:
315 315 if (level) {
316 316 #if defined(PPC_DEBUG_IRQ)
317 317 if (loglevel & CPU_LOG_INT) {
... ... @@ -321,8 +321,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
321 321 ppc40x_chip_reset(env);
322 322 }
323 323 break;
324   - /* No break here */
325   - case PPC405_INPUT_RESET_CORE:
  324 + case PPC40x_INPUT_RESET_CORE:
326 325 /* XXX: TODO: update DBSR[MRR] */
327 326 if (level) {
328 327 #if defined(PPC_DEBUG_IRQ)
... ... @@ -333,7 +332,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
333 332 ppc40x_core_reset(env);
334 333 }
335 334 break;
336   - case PPC405_INPUT_CINT:
  335 + case PPC40x_INPUT_CINT:
337 336 /* Level sensitive - active high */
338 337 #if defined(PPC_DEBUG_IRQ)
339 338 if (loglevel & CPU_LOG_INT) {
... ... @@ -341,10 +340,9 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
341 340 __func__, level);
342 341 }
343 342 #endif
344   - /* XXX: TOFIX */
345   - ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
  343 + ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
346 344 break;
347   - case PPC405_INPUT_INT:
  345 + case PPC40x_INPUT_INT:
348 346 /* Level sensitive - active high */
349 347 #if defined(PPC_DEBUG_IRQ)
350 348 if (loglevel & CPU_LOG_INT) {
... ... @@ -354,7 +352,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
354 352 #endif
355 353 ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
356 354 break;
357   - case PPC405_INPUT_HALT:
  355 + case PPC40x_INPUT_HALT:
358 356 /* Level sensitive - active low */
359 357 if (level) {
360 358 #if defined(PPC_DEBUG_IRQ)
... ... @@ -372,7 +370,7 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
372 370 env->halted = 0;
373 371 }
374 372 break;
375   - case PPC405_INPUT_DEBUG:
  373 + case PPC40x_INPUT_DEBUG:
376 374 /* Level sensitive - active high */
377 375 #if defined(PPC_DEBUG_IRQ)
378 376 if (loglevel & CPU_LOG_INT) {
... ... @@ -398,9 +396,10 @@ static void ppc405_set_irq (void *opaque, int pin, int level)
398 396 }
399 397 }
400 398  
401   -void ppc405_irq_init (CPUState *env)
  399 +void ppc40x_irq_init (CPUState *env)
402 400 {
403   - env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
  401 + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
  402 + env, PPC40x_INPUT_NB);
404 403 }
405 404  
406 405 /*****************************************************************************/
... ...
target-ppc/cpu.h
  View file @4e290a0
... ... @@ -1117,23 +1117,15 @@ enum {
1117 1117 };
1118 1118  
1119 1119 enum {
1120   - /* PowerPC 401/403 input pins */
1121   - PPC401_INPUT_RESET = 0,
1122   - PPC401_INPUT_CINT = 1,
1123   - PPC401_INPUT_INT = 2,
1124   - PPC401_INPUT_BERR = 3,
1125   - PPC401_INPUT_HALT = 4,
1126   -};
1127   -
1128   -enum {
1129   - /* PowerPC 405 input pins */
1130   - PPC405_INPUT_RESET_CORE = 0,
1131   - PPC405_INPUT_RESET_CHIP = 1,
1132   - PPC405_INPUT_RESET_SYS = 2,
1133   - PPC405_INPUT_CINT = 3,
1134   - PPC405_INPUT_INT = 4,
1135   - PPC405_INPUT_HALT = 5,
1136   - PPC405_INPUT_DEBUG = 6,
  1120 + /* PowerPC 40x input pins */
  1121 + PPC40x_INPUT_RESET_CORE = 0,
  1122 + PPC40x_INPUT_RESET_CHIP = 1,
  1123 + PPC40x_INPUT_RESET_SYS = 2,
  1124 + PPC40x_INPUT_CINT = 3,
  1125 + PPC40x_INPUT_INT = 4,
  1126 + PPC40x_INPUT_HALT = 5,
  1127 + PPC40x_INPUT_DEBUG = 6,
  1128 + PPC40x_INPUT_NB,
1137 1129 };
1138 1130  
1139 1131 enum {
... ...
target-ppc/translate_init.c
  View file @4e290a0
... ... @@ -54,8 +54,7 @@ static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
54 54 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
55 55 #endif
56 56  
57   -PPC_IRQ_INIT_FN(401);
58   -PPC_IRQ_INIT_FN(405);
  57 +PPC_IRQ_INIT_FN(40x);
59 58 PPC_IRQ_INIT_FN(6xx);
60 59 PPC_IRQ_INIT_FN(970);
61 60  
... ... @@ -2482,7 +2481,8 @@ static void init_proc_401 (CPUPPCState *env)
2482 2481 &spr_read_generic, &spr_write_generic,
2483 2482 0x00000000);
2484 2483 init_excp_4xx_real(env);
2485   - /* XXX: TODO: allocate internal IRQ controller */
  2484 + /* Allocate hardware IRQ controller */
  2485 + ppc40x_irq_init(env);
2486 2486 }
2487 2487  
2488 2488 /* PowerPC 401x2 */
... ... @@ -2518,7 +2518,8 @@ static void init_proc_401x2 (CPUPPCState *env)
2518 2518 env->nb_ways = 1;
2519 2519 env->id_tlbs = 0;
2520 2520 init_excp_4xx_softmmu(env);
2521   - /* XXX: TODO: allocate internal IRQ controller */
  2521 + /* Allocate hardware IRQ controller */
  2522 + ppc40x_irq_init(env);
2522 2523 }
2523 2524  
2524 2525 /* PowerPC 401x3 */
... ... @@ -2536,7 +2537,14 @@ static void init_proc_401x2 (CPUPPCState *env)
2536 2537  
2537 2538 static void init_proc_401x3 (CPUPPCState *env)
2538 2539 {
  2540 + gen_spr_40x(env);
  2541 + gen_spr_401_403(env);
  2542 + gen_spr_401(env);
  2543 + gen_spr_401x2(env);
  2544 + gen_spr_compress(env);
2539 2545 init_excp_4xx_softmmu(env);
  2546 + /* Allocate hardware IRQ controller */
  2547 + ppc40x_irq_init(env);
2540 2548 }
2541 2549 #endif /* TODO */
2542 2550  
... ... @@ -2573,7 +2581,8 @@ static void init_proc_IOP480 (CPUPPCState *env)
2573 2581 env->nb_ways = 1;
2574 2582 env->id_tlbs = 0;
2575 2583 init_excp_4xx_softmmu(env);
2576   - /* XXX: TODO: allocate internal IRQ controller */
  2584 + /* Allocate hardware IRQ controller */
  2585 + ppc40x_irq_init(env);
2577 2586 }
2578 2587  
2579 2588 /* PowerPC 403 */
... ... @@ -2594,7 +2603,8 @@ static void init_proc_403 (CPUPPCState *env)
2594 2603 gen_spr_403(env);
2595 2604 gen_spr_403_real(env);
2596 2605 init_excp_4xx_real(env);
2597   - /* XXX: TODO: allocate internal IRQ controller */
  2606 + /* Allocate hardware IRQ controller */
  2607 + ppc40x_irq_init(env);
2598 2608 }
2599 2609  
2600 2610 /* PowerPC 403 GCX */
... ... @@ -2630,7 +2640,8 @@ static void init_proc_403GCX (CPUPPCState *env)
2630 2640 env->nb_ways = 1;
2631 2641 env->id_tlbs = 0;
2632 2642 init_excp_4xx_softmmu(env);
2633   - /* XXX: TODO: allocate internal IRQ controller */
  2643 + /* Allocate hardware IRQ controller */
  2644 + ppc40x_irq_init(env);
2634 2645 }
2635 2646  
2636 2647 /* PowerPC 405 */
... ... @@ -2667,7 +2678,7 @@ static void init_proc_405 (CPUPPCState *env)
2667 2678 env->id_tlbs = 0;
2668 2679 init_excp_4xx_softmmu(env);
2669 2680 /* Allocate hardware IRQ controller */
2670   - ppc405_irq_init(env);
  2681 + ppc40x_irq_init(env);
2671 2682 }
2672 2683  
2673 2684 /* PowerPC 440 EP */
... ...