gwj / at91sam9263 · Commits

Commit 4e12cd946f9e7a6e3d35bcce0bc7bfe38cec4eb7

Authored by Avi Kivity
Committed by Anthony Liguori
1 parent fbb7b4e0

vga: Replace VGA_COMMON with a structure 

All VGA devices share a common field subset; currently they do so by
a macro which defines the common fields inline their state structures,
relying on the the common state being placed at offset 0 in the structure.
This makes refactoring the code difficult and requires a lot of error prone
casts.

Replace the macro by a new VGACommonState structure, and the casts by
regular field access and container_of() for upcasts.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Inline Side-by-side
Showing 5 changed files with 472 additions and 472 deletions
hw/cirrus_vga.c
  View file @4e12cd9
@@ -220,12 +220,12 @@ @@ -220,12 +220,12 @@
220 ( /* check dst is within bounds */ \ 220 ( /* check dst is within bounds */ \
221 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \ 221 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
222 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \ 222 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
223 - (s)->vram_size \ 223 + (s)->vga.vram_size \
224 ) || \ 224 ) || \
225 ( /* check src is within bounds */ \ 225 ( /* check src is within bounds */ \
226 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \ 226 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
227 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \ 227 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
228 - (s)->vram_size \ 228 + (s)->vga.vram_size \
229 ) \ 229 ) \
230 ) 230 )
231 231
@@ -238,7 +238,7 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, @@ -238,7 +238,7 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
238 uint8_t *dst, int dst_pitch, int width, int height); 238 uint8_t *dst, int dst_pitch, int width, int height);
239 239
240 typedef struct CirrusVGAState { 240 typedef struct CirrusVGAState {
241 - VGA_STATE_COMMON 241 + VGACommonState vga;
242 242
243 int cirrus_linear_io_addr; 243 int cirrus_linear_io_addr;
244 int cirrus_linear_bitblt_io_addr; 244 int cirrus_linear_bitblt_io_addr;
@@ -599,17 +599,17 @@ static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) @@ -599,17 +599,17 @@ static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
599 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; 599 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
600 break; 600 break;
601 case 2: 601 case 2:
602 - color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8); 602 + color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
603 s->cirrus_blt_fgcol = le16_to_cpu(color); 603 s->cirrus_blt_fgcol = le16_to_cpu(color);
604 break; 604 break;
605 case 3: 605 case 3:
606 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | 606 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
607 - (s->gr[0x11] << 8) | (s->gr[0x13] << 16); 607 + (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
608 break; 608 break;
609 default: 609 default:
610 case 4: 610 case 4:
611 - color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |  
612 - (s->gr[0x13] << 16) | (s->gr[0x15] << 24); 611 + color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
  612 + (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
613 s->cirrus_blt_fgcol = le32_to_cpu(color); 613 s->cirrus_blt_fgcol = le32_to_cpu(color);
614 break; 614 break;
615 } 615 }
@@ -623,17 +623,17 @@ static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) @@ -623,17 +623,17 @@ static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
623 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; 623 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
624 break; 624 break;
625 case 2: 625 case 2:
626 - color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8); 626 + color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
627 s->cirrus_blt_bgcol = le16_to_cpu(color); 627 s->cirrus_blt_bgcol = le16_to_cpu(color);
628 break; 628 break;
629 case 3: 629 case 3:
630 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | 630 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
631 - (s->gr[0x10] << 8) | (s->gr[0x12] << 16); 631 + (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
632 break; 632 break;
633 default: 633 default:
634 case 4: 634 case 4:
635 - color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |  
636 - (s->gr[0x12] << 16) | (s->gr[0x14] << 24); 635 + color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
  636 + (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
637 s->cirrus_blt_bgcol = le32_to_cpu(color); 637 s->cirrus_blt_bgcol = le32_to_cpu(color);
638 break; 638 break;
639 } 639 }
@@ -652,7 +652,7 @@ static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, @@ -652,7 +652,7 @@ static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
652 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; 652 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
653 off_cur &= TARGET_PAGE_MASK; 653 off_cur &= TARGET_PAGE_MASK;
654 while (off_cur < off_cur_end) { 654 while (off_cur < off_cur_end) {
655 - cpu_physical_memory_set_dirty(s->vram_offset + off_cur); 655 + cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
656 off_cur += TARGET_PAGE_SIZE; 656 off_cur += TARGET_PAGE_SIZE;
657 } 657 }
658 off_begin += off_pitch; 658 off_begin += off_pitch;
@@ -664,7 +664,7 @@ static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, @@ -664,7 +664,7 @@ static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
664 { 664 {
665 uint8_t *dst; 665 uint8_t *dst;
666 666
667 - dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask); 667 + dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
668 668
669 if (BLTUNSAFE(s)) 669 if (BLTUNSAFE(s))
670 return 0; 670 return 0;
@@ -687,7 +687,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) @@ -687,7 +687,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
687 if (BLTUNSAFE(s)) 687 if (BLTUNSAFE(s))
688 return 0; 688 return 0;
689 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; 689 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
690 - rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), 690 + rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
691 s->cirrus_blt_dstpitch, 691 s->cirrus_blt_dstpitch,
692 s->cirrus_blt_width, s->cirrus_blt_height); 692 s->cirrus_blt_width, s->cirrus_blt_height);
693 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 693 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
@@ -706,7 +706,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) @@ -706,7 +706,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
706 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) 706 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
707 { 707 {
708 return cirrus_bitblt_common_patterncopy(s, 708 return cirrus_bitblt_common_patterncopy(s,
709 - s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) & 709 + s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
710 s->cirrus_addr_mask)); 710 s->cirrus_addr_mask));
711 } 711 }
712 712
@@ -718,8 +718,8 @@ static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) @@ -718,8 +718,8 @@ static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
718 int depth; 718 int depth;
719 int notify = 0; 719 int notify = 0;
720 720
721 - depth = s->get_bpp((VGAState *)s) / 8;  
722 - s->get_resolution((VGAState *)s, &width, &height); 721 + depth = s->vga.get_bpp(&s->vga) / 8;
  722 + s->vga.get_resolution(&s->vga, &width, &height);
723 723
724 /* extra x, y */ 724 /* extra x, y */
725 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; 725 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
@@ -757,15 +757,15 @@ static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) @@ -757,15 +757,15 @@ static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
757 if (notify) 757 if (notify)
758 vga_hw_update(); 758 vga_hw_update();
759 759
760 - (*s->cirrus_rop) (s, s->vram_ptr + 760 + (*s->cirrus_rop) (s, s->vga.vram_ptr +
761 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), 761 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
762 - s->vram_ptr + 762 + s->vga.vram_ptr +
763 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask), 763 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
764 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, 764 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
765 s->cirrus_blt_width, s->cirrus_blt_height); 765 s->cirrus_blt_width, s->cirrus_blt_height);
766 766
767 if (notify) 767 if (notify)
768 - qemu_console_copy(s->ds, 768 + qemu_console_copy(s->vga.ds,
769 sx, sy, dx, dy, 769 sx, sy, dx, dy,
770 s->cirrus_blt_width / depth, 770 s->cirrus_blt_width / depth,
771 s->cirrus_blt_height); 771 s->cirrus_blt_height);
@@ -783,8 +783,8 @@ static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) @@ -783,8 +783,8 @@ static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
783 if (BLTUNSAFE(s)) 783 if (BLTUNSAFE(s))
784 return 0; 784 return 0;
785 785
786 - cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,  
787 - s->cirrus_blt_srcaddr - s->start_addr, 786 + cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
  787 + s->cirrus_blt_srcaddr - s->vga.start_addr,
788 s->cirrus_blt_width, s->cirrus_blt_height); 788 s->cirrus_blt_width, s->cirrus_blt_height);
789 789
790 return 1; 790 return 1;
@@ -810,7 +810,7 @@ static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) @@ -810,7 +810,7 @@ static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
810 } else { 810 } else {
811 /* at least one scan line */ 811 /* at least one scan line */
812 do { 812 do {
813 - (*s->cirrus_rop)(s, s->vram_ptr + 813 + (*s->cirrus_rop)(s, s->vga.vram_ptr +
814 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), 814 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
815 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); 815 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
816 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0, 816 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
@@ -842,7 +842,7 @@ static void cirrus_bitblt_reset(CirrusVGAState * s) @@ -842,7 +842,7 @@ static void cirrus_bitblt_reset(CirrusVGAState * s)
842 { 842 {
843 int need_update; 843 int need_update;
844 844
845 - s->gr[0x31] &= 845 + s->vga.gr[0x31] &=
846 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); 846 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
847 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0] 847 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
848 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0]; 848 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
@@ -916,19 +916,19 @@ static void cirrus_bitblt_start(CirrusVGAState * s) @@ -916,19 +916,19 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
916 { 916 {
917 uint8_t blt_rop; 917 uint8_t blt_rop;
918 918
919 - s->gr[0x31] |= CIRRUS_BLT_BUSY; 919 + s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
920 920
921 - s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;  
922 - s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;  
923 - s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));  
924 - s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8)); 921 + s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
  922 + s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
  923 + s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
  924 + s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
925 s->cirrus_blt_dstaddr = 925 s->cirrus_blt_dstaddr =
926 - (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16)); 926 + (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
927 s->cirrus_blt_srcaddr = 927 s->cirrus_blt_srcaddr =
928 - (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));  
929 - s->cirrus_blt_mode = s->gr[0x30];  
930 - s->cirrus_blt_modeext = s->gr[0x33];  
931 - blt_rop = s->gr[0x32]; 928 + (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
  929 + s->cirrus_blt_mode = s->vga.gr[0x30];
  930 + s->cirrus_blt_modeext = s->vga.gr[0x33];
  931 + blt_rop = s->vga.gr[0x32];
932 932
933 #ifdef DEBUG_BITBLT 933 #ifdef DEBUG_BITBLT
934 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n", 934 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
@@ -941,7 +941,7 @@ static void cirrus_bitblt_start(CirrusVGAState * s) @@ -941,7 +941,7 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
941 s->cirrus_blt_srcpitch, 941 s->cirrus_blt_srcpitch,
942 s->cirrus_blt_dstaddr, 942 s->cirrus_blt_dstaddr,
943 s->cirrus_blt_srcaddr, 943 s->cirrus_blt_srcaddr,
944 - s->gr[0x2f]); 944 + s->vga.gr[0x2f]);
945 #endif 945 #endif
946 946
947 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { 947 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
@@ -1059,8 +1059,8 @@ static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) @@ -1059,8 +1059,8 @@ static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1059 { 1059 {
1060 unsigned old_value; 1060 unsigned old_value;
1061 1061
1062 - old_value = s->gr[0x31];  
1063 - s->gr[0x31] = reg_value; 1062 + old_value = s->vga.gr[0x31];
  1063 + s->vga.gr[0x31] = reg_value;
1064 1064
1065 if (((old_value & CIRRUS_BLT_RESET) != 0) && 1065 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1066 ((reg_value & CIRRUS_BLT_RESET) == 0)) { 1066 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
@@ -1083,24 +1083,24 @@ static void cirrus_get_offsets(VGAState *s1, @@ -1083,24 +1083,24 @@ static void cirrus_get_offsets(VGAState *s1,
1083 uint32_t *pstart_addr, 1083 uint32_t *pstart_addr,
1084 uint32_t *pline_compare) 1084 uint32_t *pline_compare)
1085 { 1085 {
1086 - CirrusVGAState * s = (CirrusVGAState *)s1; 1086 + CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1087 uint32_t start_addr, line_offset, line_compare; 1087 uint32_t start_addr, line_offset, line_compare;
1088 1088
1089 - line_offset = s->cr[0x13]  
1090 - | ((s->cr[0x1b] & 0x10) << 4); 1089 + line_offset = s->vga.cr[0x13]
  1090 + | ((s->vga.cr[0x1b] & 0x10) << 4);
1091 line_offset <<= 3; 1091 line_offset <<= 3;
1092 *pline_offset = line_offset; 1092 *pline_offset = line_offset;
1093 1093
1094 - start_addr = (s->cr[0x0c] << 8)  
1095 - | s->cr[0x0d]  
1096 - | ((s->cr[0x1b] & 0x01) << 16)  
1097 - | ((s->cr[0x1b] & 0x0c) << 15)  
1098 - | ((s->cr[0x1d] & 0x80) << 12); 1094 + start_addr = (s->vga.cr[0x0c] << 8)
  1095 + | s->vga.cr[0x0d]
  1096 + | ((s->vga.cr[0x1b] & 0x01) << 16)
  1097 + | ((s->vga.cr[0x1b] & 0x0c) << 15)
  1098 + | ((s->vga.cr[0x1d] & 0x80) << 12);
1099 *pstart_addr = start_addr; 1099 *pstart_addr = start_addr;
1100 1100
1101 - line_compare = s->cr[0x18] |  
1102 - ((s->cr[0x07] & 0x10) << 4) |  
1103 - ((s->cr[0x09] & 0x40) << 3); 1101 + line_compare = s->vga.cr[0x18] |
  1102 + ((s->vga.cr[0x07] & 0x10) << 4) |
  1103 + ((s->vga.cr[0x09] & 0x40) << 3);
1104 *pline_compare = line_compare; 1104 *pline_compare = line_compare;
1105 } 1105 }
1106 1106
@@ -1128,12 +1128,12 @@ static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s) @@ -1128,12 +1128,12 @@ static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1128 1128
1129 static int cirrus_get_bpp(VGAState *s1) 1129 static int cirrus_get_bpp(VGAState *s1)
1130 { 1130 {
1131 - CirrusVGAState * s = (CirrusVGAState *)s1; 1131 + CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1132 uint32_t ret = 8; 1132 uint32_t ret = 8;
1133 1133
1134 - if ((s->sr[0x07] & 0x01) != 0) { 1134 + if ((s->vga.sr[0x07] & 0x01) != 0) {
1135 /* Cirrus SVGA */ 1135 /* Cirrus SVGA */
1136 - switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) { 1136 + switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1137 case CIRRUS_SR7_BPP_8: 1137 case CIRRUS_SR7_BPP_8:
1138 ret = 8; 1138 ret = 8;
1139 break; 1139 break;
@@ -1151,7 +1151,7 @@ static int cirrus_get_bpp(VGAState *s1) @@ -1151,7 +1151,7 @@ static int cirrus_get_bpp(VGAState *s1)
1151 break; 1151 break;
1152 default: 1152 default:
1153 #ifdef DEBUG_CIRRUS 1153 #ifdef DEBUG_CIRRUS
1154 - printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]); 1154 + printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1155 #endif 1155 #endif
1156 ret = 8; 1156 ret = 8;
1157 break; 1157 break;
@@ -1191,12 +1191,12 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) @@ -1191,12 +1191,12 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1191 unsigned offset; 1191 unsigned offset;
1192 unsigned limit; 1192 unsigned limit;
1193 1193
1194 - if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */  
1195 - offset = s->gr[0x09 + bank_index]; 1194 + if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
  1195 + offset = s->vga.gr[0x09 + bank_index];
1196 else /* single bank */ 1196 else /* single bank */
1197 - offset = s->gr[0x09]; 1197 + offset = s->vga.gr[0x09];
1198 1198
1199 - if ((s->gr[0x0b] & 0x20) != 0) 1199 + if ((s->vga.gr[0x0b] & 0x20) != 0)
1200 offset <<= 14; 1200 offset <<= 14;
1201 else 1201 else
1202 offset <<= 12; 1202 offset <<= 12;
@@ -1206,7 +1206,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) @@ -1206,7 +1206,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1206 else 1206 else
1207 limit = s->real_vram_size - offset; 1207 limit = s->real_vram_size - offset;
1208 1208
1209 - if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { 1209 + if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1210 if (limit > 0x8000) { 1210 if (limit > 0x8000) {
1211 offset += 0x8000; 1211 offset += 0x8000;
1212 limit -= 0x8000; 1212 limit -= 0x8000;
@@ -1218,7 +1218,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) @@ -1218,7 +1218,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1218 if (limit > 0) { 1218 if (limit > 0) {
1219 /* Thinking about changing bank base? First, drop the dirty bitmap information 1219 /* Thinking about changing bank base? First, drop the dirty bitmap information
1220 * on the current location, otherwise we lose this pointer forever */ 1220 * on the current location, otherwise we lose this pointer forever */
1221 - if (s->lfb_vram_mapped) { 1221 + if (s->vga.lfb_vram_mapped) {
1222 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000; 1222 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1223 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000); 1223 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1224 } 1224 }
@@ -1247,7 +1247,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value) @@ -1247,7 +1247,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1247 case 0x04: // Standard VGA 1247 case 0x04: // Standard VGA
1248 return CIRRUS_HOOK_NOT_HANDLED; 1248 return CIRRUS_HOOK_NOT_HANDLED;
1249 case 0x06: // Unlock Cirrus extensions 1249 case 0x06: // Unlock Cirrus extensions
1250 - *reg_value = s->sr[reg_index]; 1250 + *reg_value = s->vga.sr[reg_index];
1251 break; 1251 break;
1252 case 0x10: 1252 case 0x10:
1253 case 0x30: 1253 case 0x30:
@@ -1257,7 +1257,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value) @@ -1257,7 +1257,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1257 case 0xb0: 1257 case 0xb0:
1258 case 0xd0: 1258 case 0xd0:
1259 case 0xf0: // Graphics Cursor X 1259 case 0xf0: // Graphics Cursor X
1260 - *reg_value = s->sr[0x10]; 1260 + *reg_value = s->vga.sr[0x10];
1261 break; 1261 break;
1262 case 0x11: 1262 case 0x11:
1263 case 0x31: 1263 case 0x31:
@@ -1267,7 +1267,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value) @@ -1267,7 +1267,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1267 case 0xb1: 1267 case 0xb1:
1268 case 0xd1: 1268 case 0xd1:
1269 case 0xf1: // Graphics Cursor Y 1269 case 0xf1: // Graphics Cursor Y
1270 - *reg_value = s->sr[0x11]; 1270 + *reg_value = s->vga.sr[0x11];
1271 break; 1271 break;
1272 case 0x05: // ??? 1272 case 0x05: // ???
1273 case 0x07: // Extended Sequencer Mode 1273 case 0x07: // Extended Sequencer Mode
@@ -1296,7 +1296,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value) @@ -1296,7 +1296,7 @@ cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1296 #ifdef DEBUG_CIRRUS 1296 #ifdef DEBUG_CIRRUS
1297 printf("cirrus: handled inport sr_index %02x\n", reg_index); 1297 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1298 #endif 1298 #endif
1299 - *reg_value = s->sr[reg_index]; 1299 + *reg_value = s->vga.sr[reg_index];
1300 break; 1300 break;
1301 default: 1301 default:
1302 #ifdef DEBUG_CIRRUS 1302 #ifdef DEBUG_CIRRUS
@@ -1322,9 +1322,9 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) @@ -1322,9 +1322,9 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1322 case 0x06: // Unlock Cirrus extensions 1322 case 0x06: // Unlock Cirrus extensions
1323 reg_value &= 0x17; 1323 reg_value &= 0x17;
1324 if (reg_value == 0x12) { 1324 if (reg_value == 0x12) {
1325 - s->sr[reg_index] = 0x12; 1325 + s->vga.sr[reg_index] = 0x12;
1326 } else { 1326 } else {
1327 - s->sr[reg_index] = 0x0f; 1327 + s->vga.sr[reg_index] = 0x0f;
1328 } 1328 }
1329 break; 1329 break;
1330 case 0x10: 1330 case 0x10:
@@ -1335,7 +1335,7 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) @@ -1335,7 +1335,7 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1335 case 0xb0: 1335 case 0xb0:
1336 case 0xd0: 1336 case 0xd0:
1337 case 0xf0: // Graphics Cursor X 1337 case 0xf0: // Graphics Cursor X
1338 - s->sr[0x10] = reg_value; 1338 + s->vga.sr[0x10] = reg_value;
1339 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5); 1339 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1340 break; 1340 break;
1341 case 0x11: 1341 case 0x11:
@@ -1346,7 +1346,7 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) @@ -1346,7 +1346,7 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1346 case 0xb1: 1346 case 0xb1:
1347 case 0xd1: 1347 case 0xd1:
1348 case 0xf1: // Graphics Cursor Y 1348 case 0xf1: // Graphics Cursor Y
1349 - s->sr[0x11] = reg_value; 1349 + s->vga.sr[0x11] = reg_value;
1350 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5); 1350 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1351 break; 1351 break;
1352 case 0x07: // Extended Sequencer Mode 1352 case 0x07: // Extended Sequencer Mode
@@ -1372,14 +1372,14 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) @@ -1372,14 +1372,14 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1372 case 0x1d: // VCLK 2 Denominator & Post 1372 case 0x1d: // VCLK 2 Denominator & Post
1373 case 0x1e: // VCLK 3 Denominator & Post 1373 case 0x1e: // VCLK 3 Denominator & Post
1374 case 0x1f: // BIOS Write Enable and MCLK select 1374 case 0x1f: // BIOS Write Enable and MCLK select
1375 - s->sr[reg_index] = reg_value; 1375 + s->vga.sr[reg_index] = reg_value;
1376 #ifdef DEBUG_CIRRUS 1376 #ifdef DEBUG_CIRRUS
1377 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n", 1377 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1378 reg_index, reg_value); 1378 reg_index, reg_value);
1379 #endif 1379 #endif
1380 break; 1380 break;
1381 case 0x17: // Configuration Readback and Extended Control 1381 case 0x17: // Configuration Readback and Extended Control
1382 - s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7); 1382 + s->vga.sr[reg_index] = (s->vga.sr[reg_index] & 0x38) | (reg_value & 0xc7);
1383 cirrus_update_memory_access(s); 1383 cirrus_update_memory_access(s);
1384 break; 1384 break;
1385 default: 1385 default:
@@ -1427,29 +1427,29 @@ static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) @@ -1427,29 +1427,29 @@ static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1427 1427
1428 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value) 1428 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1429 { 1429 {
1430 - if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) 1430 + if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1431 return CIRRUS_HOOK_NOT_HANDLED; 1431 return CIRRUS_HOOK_NOT_HANDLED;
1432 *reg_value = 1432 *reg_value =
1433 - s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +  
1434 - s->dac_sub_index];  
1435 - if (++s->dac_sub_index == 3) {  
1436 - s->dac_sub_index = 0;  
1437 - s->dac_read_index++; 1433 + s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
  1434 + s->vga.dac_sub_index];
  1435 + if (++s->vga.dac_sub_index == 3) {
  1436 + s->vga.dac_sub_index = 0;
  1437 + s->vga.dac_read_index++;
1438 } 1438 }
1439 return CIRRUS_HOOK_HANDLED; 1439 return CIRRUS_HOOK_HANDLED;
1440 } 1440 }
1441 1441
1442 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value) 1442 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1443 { 1443 {
1444 - if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) 1444 + if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1445 return CIRRUS_HOOK_NOT_HANDLED; 1445 return CIRRUS_HOOK_NOT_HANDLED;
1446 - s->dac_cache[s->dac_sub_index] = reg_value;  
1447 - if (++s->dac_sub_index == 3) {  
1448 - memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],  
1449 - s->dac_cache, 3); 1446 + s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
  1447 + if (++s->vga.dac_sub_index == 3) {
  1448 + memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
  1449 + s->vga.dac_cache, 3);
1450 /* XXX update cursor */ 1450 /* XXX update cursor */
1451 - s->dac_sub_index = 0;  
1452 - s->dac_write_index++; 1451 + s->vga.dac_sub_index = 0;
  1452 + s->vga.dac_write_index++;
1453 } 1453 }
1454 return CIRRUS_HOOK_HANDLED; 1454 return CIRRUS_HOOK_HANDLED;
1455 } 1455 }
@@ -1483,7 +1483,7 @@ cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value) @@ -1483,7 +1483,7 @@ cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1483 } 1483 }
1484 1484
1485 if (reg_index < 0x3a) { 1485 if (reg_index < 0x3a) {
1486 - *reg_value = s->gr[reg_index]; 1486 + *reg_value = s->vga.gr[reg_index];
1487 } else { 1487 } else {
1488 #ifdef DEBUG_CIRRUS 1488 #ifdef DEBUG_CIRRUS
1489 printf("cirrus: inport gr_index %02x\n", reg_index); 1489 printf("cirrus: inport gr_index %02x\n", reg_index);
@@ -1515,18 +1515,18 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) @@ -1515,18 +1515,18 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1515 case 0x08: // Standard VGA 1515 case 0x08: // Standard VGA
1516 return CIRRUS_HOOK_NOT_HANDLED; 1516 return CIRRUS_HOOK_NOT_HANDLED;
1517 case 0x05: // Standard VGA, Cirrus extended mode 1517 case 0x05: // Standard VGA, Cirrus extended mode
1518 - s->gr[reg_index] = reg_value & 0x7f; 1518 + s->vga.gr[reg_index] = reg_value & 0x7f;
1519 cirrus_update_memory_access(s); 1519 cirrus_update_memory_access(s);
1520 break; 1520 break;
1521 case 0x09: // bank offset #0 1521 case 0x09: // bank offset #0
1522 case 0x0A: // bank offset #1 1522 case 0x0A: // bank offset #1
1523 - s->gr[reg_index] = reg_value; 1523 + s->vga.gr[reg_index] = reg_value;
1524 cirrus_update_bank_ptr(s, 0); 1524 cirrus_update_bank_ptr(s, 0);
1525 cirrus_update_bank_ptr(s, 1); 1525 cirrus_update_bank_ptr(s, 1);
1526 cirrus_update_memory_access(s); 1526 cirrus_update_memory_access(s);
1527 break; 1527 break;
1528 case 0x0B: 1528 case 0x0B:
1529 - s->gr[reg_index] = reg_value; 1529 + s->vga.gr[reg_index] = reg_value;
1530 cirrus_update_bank_ptr(s, 0); 1530 cirrus_update_bank_ptr(s, 0);
1531 cirrus_update_bank_ptr(s, 1); 1531 cirrus_update_bank_ptr(s, 1);
1532 cirrus_update_memory_access(s); 1532 cirrus_update_memory_access(s);
@@ -1553,23 +1553,23 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) @@ -1553,23 +1553,23 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1553 case 0x35: // BLT TRANSPARENT COLOR 0xff00 1553 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1554 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff 1554 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1555 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 1555 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1556 - s->gr[reg_index] = reg_value; 1556 + s->vga.gr[reg_index] = reg_value;
1557 break; 1557 break;
1558 case 0x21: // BLT WIDTH 0x001f00 1558 case 0x21: // BLT WIDTH 0x001f00
1559 case 0x23: // BLT HEIGHT 0x001f00 1559 case 0x23: // BLT HEIGHT 0x001f00
1560 case 0x25: // BLT DEST PITCH 0x001f00 1560 case 0x25: // BLT DEST PITCH 0x001f00
1561 case 0x27: // BLT SRC PITCH 0x001f00 1561 case 0x27: // BLT SRC PITCH 0x001f00
1562 - s->gr[reg_index] = reg_value & 0x1f; 1562 + s->vga.gr[reg_index] = reg_value & 0x1f;
1563 break; 1563 break;
1564 case 0x2a: // BLT DEST ADDR 0x3f0000 1564 case 0x2a: // BLT DEST ADDR 0x3f0000
1565 - s->gr[reg_index] = reg_value & 0x3f; 1565 + s->vga.gr[reg_index] = reg_value & 0x3f;
1566 /* if auto start mode, starts bit blt now */ 1566 /* if auto start mode, starts bit blt now */
1567 - if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) { 1567 + if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1568 cirrus_bitblt_start(s); 1568 cirrus_bitblt_start(s);
1569 } 1569 }
1570 break; 1570 break;
1571 case 0x2e: // BLT SRC ADDR 0x3f0000 1571 case 0x2e: // BLT SRC ADDR 0x3f0000
1572 - s->gr[reg_index] = reg_value & 0x3f; 1572 + s->vga.gr[reg_index] = reg_value & 0x3f;
1573 break; 1573 break;
1574 case 0x31: // BLT STATUS/START 1574 case 0x31: // BLT STATUS/START
1575 cirrus_write_bitblt(s, reg_value); 1575 cirrus_write_bitblt(s, reg_value);
@@ -1622,7 +1622,7 @@ cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value) @@ -1622,7 +1622,7 @@ cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1622 case 0x18: // Standard VGA 1622 case 0x18: // Standard VGA
1623 return CIRRUS_HOOK_NOT_HANDLED; 1623 return CIRRUS_HOOK_NOT_HANDLED;
1624 case 0x24: // Attribute Controller Toggle Readback (R) 1624 case 0x24: // Attribute Controller Toggle Readback (R)
1625 - *reg_value = (s->ar_flip_flop << 7); 1625 + *reg_value = (s->vga.ar_flip_flop << 7);
1626 break; 1626 break;
1627 case 0x19: // Interlace End 1627 case 0x19: // Interlace End
1628 case 0x1a: // Miscellaneous Control 1628 case 0x1a: // Miscellaneous Control
@@ -1632,10 +1632,10 @@ cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value) @@ -1632,10 +1632,10 @@ cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1632 case 0x22: // Graphics Data Latches Readback (R) 1632 case 0x22: // Graphics Data Latches Readback (R)
1633 case 0x25: // Part Status 1633 case 0x25: // Part Status
1634 case 0x27: // Part ID (R) 1634 case 0x27: // Part ID (R)
1635 - *reg_value = s->cr[reg_index]; 1635 + *reg_value = s->vga.cr[reg_index];
1636 break; 1636 break;
1637 case 0x26: // Attribute Controller Index Readback (R) 1637 case 0x26: // Attribute Controller Index Readback (R)
1638 - *reg_value = s->ar_index & 0x3f; 1638 + *reg_value = s->vga.ar_index & 0x3f;
1639 break; 1639 break;
1640 default: 1640 default:
1641 #ifdef DEBUG_CIRRUS 1641 #ifdef DEBUG_CIRRUS
@@ -1683,7 +1683,7 @@ cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value) @@ -1683,7 +1683,7 @@ cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1683 case 0x1b: // Extended Display Control 1683 case 0x1b: // Extended Display Control
1684 case 0x1c: // Sync Adjust and Genlock 1684 case 0x1c: // Sync Adjust and Genlock
1685 case 0x1d: // Overlay Extended Control 1685 case 0x1d: // Overlay Extended Control
1686 - s->cr[reg_index] = reg_value; 1686 + s->vga.cr[reg_index] = reg_value;
1687 #ifdef DEBUG_CIRRUS 1687 #ifdef DEBUG_CIRRUS
1688 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n", 1688 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1689 reg_index, reg_value); 1689 reg_index, reg_value);
@@ -1946,7 +1946,7 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, @@ -1946,7 +1946,7 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1946 unsigned val = mem_value; 1946 unsigned val = mem_value;
1947 uint8_t *dst; 1947 uint8_t *dst;
1948 1948
1949 - dst = s->vram_ptr + (offset &= s->cirrus_addr_mask); 1949 + dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1950 for (x = 0; x < 8; x++) { 1950 for (x = 0; x < 8; x++) {
1951 if (val & 0x80) { 1951 if (val & 0x80) {
1952 *dst = s->cirrus_shadow_gr1; 1952 *dst = s->cirrus_shadow_gr1;
@@ -1956,8 +1956,8 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, @@ -1956,8 +1956,8 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1956 val <<= 1; 1956 val <<= 1;
1957 dst++; 1957 dst++;
1958 } 1958 }
1959 - cpu_physical_memory_set_dirty(s->vram_offset + offset);  
1960 - cpu_physical_memory_set_dirty(s->vram_offset + offset + 7); 1959 + cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
  1960 + cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
1961 } 1961 }
1962 1962
1963 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, 1963 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
@@ -1969,20 +1969,20 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, @@ -1969,20 +1969,20 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1969 unsigned val = mem_value; 1969 unsigned val = mem_value;
1970 uint8_t *dst; 1970 uint8_t *dst;
1971 1971
1972 - dst = s->vram_ptr + (offset &= s->cirrus_addr_mask); 1972 + dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1973 for (x = 0; x < 8; x++) { 1973 for (x = 0; x < 8; x++) {
1974 if (val & 0x80) { 1974 if (val & 0x80) {
1975 *dst = s->cirrus_shadow_gr1; 1975 *dst = s->cirrus_shadow_gr1;
1976 - *(dst + 1) = s->gr[0x11]; 1976 + *(dst + 1) = s->vga.gr[0x11];
1977 } else if (mode == 5) { 1977 } else if (mode == 5) {
1978 *dst = s->cirrus_shadow_gr0; 1978 *dst = s->cirrus_shadow_gr0;
1979 - *(dst + 1) = s->gr[0x10]; 1979 + *(dst + 1) = s->vga.gr[0x10];
1980 } 1980 }
1981 val <<= 1; 1981 val <<= 1;
1982 dst += 2; 1982 dst += 2;
1983 } 1983 }
1984 - cpu_physical_memory_set_dirty(s->vram_offset + offset);  
1985 - cpu_physical_memory_set_dirty(s->vram_offset + offset + 15); 1984 + cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
  1985 + cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
1986 } 1986 }
1987 1987
1988 /*************************************** 1988 /***************************************
@@ -1998,7 +1998,7 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) @@ -1998,7 +1998,7 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1998 unsigned bank_offset; 1998 unsigned bank_offset;
1999 uint32_t val; 1999 uint32_t val;
2000 2000
2001 - if ((s->sr[0x07] & 0x01) == 0) { 2001 + if ((s->vga.sr[0x07] & 0x01) == 0) {
2002 return vga_mem_readb(s, addr); 2002 return vga_mem_readb(s, addr);
2003 } 2003 }
2004 2004
@@ -2011,19 +2011,19 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) @@ -2011,19 +2011,19 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2011 bank_offset = addr & 0x7fff; 2011 bank_offset = addr & 0x7fff;
2012 if (bank_offset < s->cirrus_bank_limit[bank_index]) { 2012 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2013 bank_offset += s->cirrus_bank_base[bank_index]; 2013 bank_offset += s->cirrus_bank_base[bank_index];
2014 - if ((s->gr[0x0B] & 0x14) == 0x14) { 2014 + if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2015 bank_offset <<= 4; 2015 bank_offset <<= 4;
2016 - } else if (s->gr[0x0B] & 0x02) { 2016 + } else if (s->vga.gr[0x0B] & 0x02) {
2017 bank_offset <<= 3; 2017 bank_offset <<= 3;
2018 } 2018 }
2019 bank_offset &= s->cirrus_addr_mask; 2019 bank_offset &= s->cirrus_addr_mask;
2020 - val = *(s->vram_ptr + bank_offset); 2020 + val = *(s->vga.vram_ptr + bank_offset);
2021 } else 2021 } else
2022 val = 0xff; 2022 val = 0xff;
2023 } else if (addr >= 0x18000 && addr < 0x18100) { 2023 } else if (addr >= 0x18000 && addr < 0x18100) {
2024 /* memory-mapped I/O */ 2024 /* memory-mapped I/O */
2025 val = 0xff; 2025 val = 0xff;
2026 - if ((s->sr[0x17] & 0x44) == 0x04) { 2026 + if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2027 val = cirrus_mmio_blt_read(s, addr & 0xff); 2027 val = cirrus_mmio_blt_read(s, addr & 0xff);
2028 } 2028 }
2029 } else { 2029 } else {
@@ -2073,7 +2073,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, @@ -2073,7 +2073,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2073 unsigned bank_offset; 2073 unsigned bank_offset;
2074 unsigned mode; 2074 unsigned mode;
2075 2075
2076 - if ((s->sr[0x07] & 0x01) == 0) { 2076 + if ((s->vga.sr[0x07] & 0x01) == 0) {
2077 vga_mem_writeb(s, addr, mem_value); 2077 vga_mem_writeb(s, addr, mem_value);
2078 return; 2078 return;
2079 } 2079 }
@@ -2093,19 +2093,19 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, @@ -2093,19 +2093,19 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2093 bank_offset = addr & 0x7fff; 2093 bank_offset = addr & 0x7fff;
2094 if (bank_offset < s->cirrus_bank_limit[bank_index]) { 2094 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2095 bank_offset += s->cirrus_bank_base[bank_index]; 2095 bank_offset += s->cirrus_bank_base[bank_index];
2096 - if ((s->gr[0x0B] & 0x14) == 0x14) { 2096 + if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2097 bank_offset <<= 4; 2097 bank_offset <<= 4;
2098 - } else if (s->gr[0x0B] & 0x02) { 2098 + } else if (s->vga.gr[0x0B] & 0x02) {
2099 bank_offset <<= 3; 2099 bank_offset <<= 3;
2100 } 2100 }
2101 bank_offset &= s->cirrus_addr_mask; 2101 bank_offset &= s->cirrus_addr_mask;
2102 - mode = s->gr[0x05] & 0x7;  
2103 - if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {  
2104 - *(s->vram_ptr + bank_offset) = mem_value;  
2105 - cpu_physical_memory_set_dirty(s->vram_offset + 2102 + mode = s->vga.gr[0x05] & 0x7;
  2103 + if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
  2104 + *(s->vga.vram_ptr + bank_offset) = mem_value;
  2105 + cpu_physical_memory_set_dirty(s->vga.vram_offset +
2106 bank_offset); 2106 bank_offset);
2107 } else { 2107 } else {
2108 - if ((s->gr[0x0B] & 0x14) != 0x14) { 2108 + if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2109 cirrus_mem_writeb_mode4and5_8bpp(s, mode, 2109 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2110 bank_offset, 2110 bank_offset,
2111 mem_value); 2111 mem_value);
@@ -2119,7 +2119,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, @@ -2119,7 +2119,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2119 } 2119 }
2120 } else if (addr >= 0x18000 && addr < 0x18100) { 2120 } else if (addr >= 0x18000 && addr < 0x18100) {
2121 /* memory-mapped I/O */ 2121 /* memory-mapped I/O */
2122 - if ((s->sr[0x17] & 0x44) == 0x04) { 2122 + if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2123 cirrus_mmio_blt_write(s, addr & 0xff, mem_value); 2123 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2124 } 2124 }
2125 } else { 2125 } else {
@@ -2176,7 +2176,7 @@ static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = { @@ -2176,7 +2176,7 @@ static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2176 static inline void invalidate_cursor1(CirrusVGAState *s) 2176 static inline void invalidate_cursor1(CirrusVGAState *s)
2177 { 2177 {
2178 if (s->last_hw_cursor_size) { 2178 if (s->last_hw_cursor_size) {
2179 - vga_invalidate_scanlines((VGAState *)s, 2179 + vga_invalidate_scanlines(&s->vga,
2180 s->last_hw_cursor_y + s->last_hw_cursor_y_start, 2180 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2181 s->last_hw_cursor_y + s->last_hw_cursor_y_end); 2181 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2182 } 2182 }
@@ -2188,9 +2188,9 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) @@ -2188,9 +2188,9 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2188 uint32_t content; 2188 uint32_t content;
2189 int y, y_min, y_max; 2189 int y, y_min, y_max;
2190 2190
2191 - src = s->vram_ptr + s->real_vram_size - 16 * 1024;  
2192 - if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {  
2193 - src += (s->sr[0x13] & 0x3c) * 256; 2191 + src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
  2192 + if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
  2193 + src += (s->vga.sr[0x13] & 0x3c) * 256;
2194 y_min = 64; 2194 y_min = 64;
2195 y_max = -1; 2195 y_max = -1;
2196 for(y = 0; y < 64; y++) { 2196 for(y = 0; y < 64; y++) {
@@ -2207,7 +2207,7 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) @@ -2207,7 +2207,7 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2207 src += 16; 2207 src += 16;
2208 } 2208 }
2209 } else { 2209 } else {
2210 - src += (s->sr[0x13] & 0x3f) * 256; 2210 + src += (s->vga.sr[0x13] & 0x3f) * 256;
2211 y_min = 32; 2211 y_min = 32;
2212 y_max = -1; 2212 y_max = -1;
2213 for(y = 0; y < 32; y++) { 2213 for(y = 0; y < 32; y++) {
@@ -2235,13 +2235,13 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) @@ -2235,13 +2235,13 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2235 update the cursor only if it moves. */ 2235 update the cursor only if it moves. */
2236 static void cirrus_cursor_invalidate(VGAState *s1) 2236 static void cirrus_cursor_invalidate(VGAState *s1)
2237 { 2237 {
2238 - CirrusVGAState *s = (CirrusVGAState *)s1; 2238 + CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2239 int size; 2239 int size;
2240 2240
2241 - if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW)) { 2241 + if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2242 size = 0; 2242 size = 0;
2243 } else { 2243 } else {
2244 - if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) 2244 + if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2245 size = 64; 2245 size = 64;
2246 else 2246 else
2247 size = 32; 2247 size = 32;
@@ -2264,16 +2264,16 @@ static void cirrus_cursor_invalidate(VGAState *s1) @@ -2264,16 +2264,16 @@ static void cirrus_cursor_invalidate(VGAState *s1)
2264 2264
2265 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y) 2265 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2266 { 2266 {
2267 - CirrusVGAState *s = (CirrusVGAState *)s1; 2267 + CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2268 int w, h, bpp, x1, x2, poffset; 2268 int w, h, bpp, x1, x2, poffset;
2269 unsigned int color0, color1; 2269 unsigned int color0, color1;
2270 const uint8_t *palette, *src; 2270 const uint8_t *palette, *src;
2271 uint32_t content; 2271 uint32_t content;
2272 2272
2273 - if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW)) 2273 + if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2274 return; 2274 return;
2275 /* fast test to see if the cursor intersects with the scan line */ 2275 /* fast test to see if the cursor intersects with the scan line */
2276 - if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) { 2276 + if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2277 h = 64; 2277 h = 64;
2278 } else { 2278 } else {
2279 h = 32; 2279 h = 32;
@@ -2282,9 +2282,9 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y) @@ -2282,9 +2282,9 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2282 scr_y >= (s->hw_cursor_y + h)) 2282 scr_y >= (s->hw_cursor_y + h))
2283 return; 2283 return;
2284 2284
2285 - src = s->vram_ptr + s->real_vram_size - 16 * 1024;  
2286 - if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {  
2287 - src += (s->sr[0x13] & 0x3c) * 256; 2285 + src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
  2286 + if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
  2287 + src += (s->vga.sr[0x13] & 0x3c) * 256;
2288 src += (scr_y - s->hw_cursor_y) * 16; 2288 src += (scr_y - s->hw_cursor_y) * 16;
2289 poffset = 8; 2289 poffset = 8;
2290 content = ((uint32_t *)src)[0] | 2290 content = ((uint32_t *)src)[0] |
@@ -2292,7 +2292,7 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y) @@ -2292,7 +2292,7 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2292 ((uint32_t *)src)[2] | 2292 ((uint32_t *)src)[2] |
2293 ((uint32_t *)src)[3]; 2293 ((uint32_t *)src)[3];
2294 } else { 2294 } else {
2295 - src += (s->sr[0x13] & 0x3f) * 256; 2295 + src += (s->vga.sr[0x13] & 0x3f) * 256;
2296 src += (scr_y - s->hw_cursor_y) * 4; 2296 src += (scr_y - s->hw_cursor_y) * 4;
2297 poffset = 128; 2297 poffset = 128;
2298 content = ((uint32_t *)src)[0] | 2298 content = ((uint32_t *)src)[0] |
@@ -2304,22 +2304,22 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y) @@ -2304,22 +2304,22 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2304 w = h; 2304 w = h;
2305 2305
2306 x1 = s->hw_cursor_x; 2306 x1 = s->hw_cursor_x;
2307 - if (x1 >= s->last_scr_width) 2307 + if (x1 >= s->vga.last_scr_width)
2308 return; 2308 return;
2309 x2 = s->hw_cursor_x + w; 2309 x2 = s->hw_cursor_x + w;
2310 - if (x2 > s->last_scr_width)  
2311 - x2 = s->last_scr_width; 2310 + if (x2 > s->vga.last_scr_width)
  2311 + x2 = s->vga.last_scr_width;
2312 w = x2 - x1; 2312 w = x2 - x1;
2313 palette = s->cirrus_hidden_palette; 2313 palette = s->cirrus_hidden_palette;
2314 - color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),  
2315 - c6_to_8(palette[0x0 * 3 + 1]),  
2316 - c6_to_8(palette[0x0 * 3 + 2]));  
2317 - color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),  
2318 - c6_to_8(palette[0xf * 3 + 1]),  
2319 - c6_to_8(palette[0xf * 3 + 2]));  
2320 - bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); 2314 + color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
  2315 + c6_to_8(palette[0x0 * 3 + 1]),
  2316 + c6_to_8(palette[0x0 * 3 + 2]));
  2317 + color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
  2318 + c6_to_8(palette[0xf * 3 + 1]),
  2319 + c6_to_8(palette[0xf * 3 + 2]));
  2320 + bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2321 d1 += x1 * bpp; 2321 d1 += x1 * bpp;
2322 - switch(ds_get_bits_per_pixel(s->ds)) { 2322 + switch(ds_get_bits_per_pixel(s->vga.ds)) {
2323 default: 2323 default:
2324 break; 2324 break;
2325 case 8: 2325 case 8:
@@ -2350,7 +2350,7 @@ static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) @@ -2350,7 +2350,7 @@ static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2350 2350
2351 addr &= s->cirrus_addr_mask; 2351 addr &= s->cirrus_addr_mask;
2352 2352
2353 - if (((s->sr[0x17] & 0x44) == 0x44) && 2353 + if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2354 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { 2354 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2355 /* memory-mapped I/O */ 2355 /* memory-mapped I/O */
2356 ret = cirrus_mmio_blt_read(s, addr & 0xff); 2356 ret = cirrus_mmio_blt_read(s, addr & 0xff);
@@ -2359,13 +2359,13 @@ static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) @@ -2359,13 +2359,13 @@ static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2359 ret = 0xff; 2359 ret = 0xff;
2360 } else { 2360 } else {
2361 /* video memory */ 2361 /* video memory */
2362 - if ((s->gr[0x0B] & 0x14) == 0x14) { 2362 + if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2363 addr <<= 4; 2363 addr <<= 4;
2364 - } else if (s->gr[0x0B] & 0x02) { 2364 + } else if (s->vga.gr[0x0B] & 0x02) {
2365 addr <<= 3; 2365 addr <<= 3;
2366 } 2366 }
2367 addr &= s->cirrus_addr_mask; 2367 addr &= s->cirrus_addr_mask;
2368 - ret = *(s->vram_ptr + addr); 2368 + ret = *(s->vga.vram_ptr + addr);
2369 } 2369 }
2370 2370
2371 return ret; 2371 return ret;
@@ -2409,7 +2409,7 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, @@ -2409,7 +2409,7 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2409 2409
2410 addr &= s->cirrus_addr_mask; 2410 addr &= s->cirrus_addr_mask;
2411 2411
2412 - if (((s->sr[0x17] & 0x44) == 0x44) && 2412 + if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2413 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { 2413 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2414 /* memory-mapped I/O */ 2414 /* memory-mapped I/O */
2415 cirrus_mmio_blt_write(s, addr & 0xff, val); 2415 cirrus_mmio_blt_write(s, addr & 0xff, val);
@@ -2421,19 +2421,19 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, @@ -2421,19 +2421,19 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2421 } 2421 }
2422 } else { 2422 } else {
2423 /* video memory */ 2423 /* video memory */
2424 - if ((s->gr[0x0B] & 0x14) == 0x14) { 2424 + if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2425 addr <<= 4; 2425 addr <<= 4;
2426 - } else if (s->gr[0x0B] & 0x02) { 2426 + } else if (s->vga.gr[0x0B] & 0x02) {
2427 addr <<= 3; 2427 addr <<= 3;
2428 } 2428 }
2429 addr &= s->cirrus_addr_mask; 2429 addr &= s->cirrus_addr_mask;
2430 2430
2431 - mode = s->gr[0x05] & 0x7;  
2432 - if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {  
2433 - *(s->vram_ptr + addr) = (uint8_t) val;  
2434 - cpu_physical_memory_set_dirty(s->vram_offset + addr); 2431 + mode = s->vga.gr[0x05] & 0x7;
  2432 + if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
  2433 + *(s->vga.vram_ptr + addr) = (uint8_t) val;
  2434 + cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
2435 } else { 2435 } else {
2436 - if ((s->gr[0x0B] & 0x14) != 0x14) { 2436 + if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2437 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); 2437 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2438 } else { 2438 } else {
2439 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); 2439 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
@@ -2586,44 +2586,44 @@ static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = { @@ -2586,44 +2586,44 @@ static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2586 2586
2587 static void map_linear_vram(CirrusVGAState *s) 2587 static void map_linear_vram(CirrusVGAState *s)
2588 { 2588 {
2589 - if (!s->map_addr && s->lfb_addr && s->lfb_end) {  
2590 - s->map_addr = s->lfb_addr;  
2591 - s->map_end = s->lfb_end;  
2592 - cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset); 2589 + if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
  2590 + s->vga.map_addr = s->vga.lfb_addr;
  2591 + s->vga.map_end = s->vga.lfb_end;
  2592 + cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2593 } 2593 }
2594 2594
2595 - if (!s->map_addr) 2595 + if (!s->vga.map_addr)
2596 return; 2596 return;
2597 2597
2598 - s->lfb_vram_mapped = 0; 2598 + s->vga.lfb_vram_mapped = 0;
2599 2599
2600 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end) 2600 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2601 - && !((s->sr[0x07] & 0x01) == 0)  
2602 - && !((s->gr[0x0B] & 0x14) == 0x14)  
2603 - && !(s->gr[0x0B] & 0x02)) { 2601 + && !((s->vga.sr[0x07] & 0x01) == 0)
  2602 + && !((s->vga.gr[0x0B] & 0x14) == 0x14)
  2603 + && !(s->vga.gr[0x0B] & 0x02)) {
2604 2604
2605 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, 2605 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2606 - (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM); 2606 + (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2607 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, 2607 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2608 - (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM); 2608 + (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2609 2609
2610 - s->lfb_vram_mapped = 1; 2610 + s->vga.lfb_vram_mapped = 1;
2611 } 2611 }
2612 else { 2612 else {
2613 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000, 2613 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2614 - s->vga_io_memory); 2614 + s->vga.vga_io_memory);
2615 } 2615 }
2616 2616
2617 - vga_dirty_log_start((VGAState *)s); 2617 + vga_dirty_log_start(&s->vga);
2618 } 2618 }
2619 2619
2620 static void unmap_linear_vram(CirrusVGAState *s) 2620 static void unmap_linear_vram(CirrusVGAState *s)
2621 { 2621 {
2622 - if (s->map_addr && s->lfb_addr && s->lfb_end)  
2623 - s->map_addr = s->map_end = 0; 2622 + if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
  2623 + s->vga.map_addr = s->vga.map_end = 0;
2624 2624
2625 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000, 2625 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2626 - s->vga_io_memory); 2626 + s->vga.vga_io_memory);
2627 } 2627 }
2628 2628
2629 /* Compute the memory access functions */ 2629 /* Compute the memory access functions */
@@ -2631,19 +2631,19 @@ static void cirrus_update_memory_access(CirrusVGAState *s) @@ -2631,19 +2631,19 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
2631 { 2631 {
2632 unsigned mode; 2632 unsigned mode;
2633 2633
2634 - if ((s->sr[0x17] & 0x44) == 0x44) { 2634 + if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2635 goto generic_io; 2635 goto generic_io;
2636 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { 2636 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2637 goto generic_io; 2637 goto generic_io;
2638 } else { 2638 } else {
2639 - if ((s->gr[0x0B] & 0x14) == 0x14) { 2639 + if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2640 goto generic_io; 2640 goto generic_io;
2641 - } else if (s->gr[0x0B] & 0x02) { 2641 + } else if (s->vga.gr[0x0B] & 0x02) {
2642 goto generic_io; 2642 goto generic_io;
2643 } 2643 }
2644 2644
2645 - mode = s->gr[0x05] & 0x7;  
2646 - if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { 2645 + mode = s->vga.gr[0x05] & 0x7;
  2646 + if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2647 map_linear_vram(s); 2647 map_linear_vram(s);
2648 } else { 2648 } else {
2649 generic_io: 2649 generic_io:
@@ -2661,94 +2661,94 @@ static uint32_t vga_ioport_read(void *opaque, uint32_t addr) @@ -2661,94 +2661,94 @@ static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2661 int val, index; 2661 int val, index;
2662 2662
2663 /* check port range access depending on color/monochrome mode */ 2663 /* check port range access depending on color/monochrome mode */
2664 - if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) 2664 + if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
2665 || (addr >= 0x3d0 && addr <= 0x3df 2665 || (addr >= 0x3d0 && addr <= 0x3df
2666 - && !(s->msr & MSR_COLOR_EMULATION))) { 2666 + && !(s->vga.msr & MSR_COLOR_EMULATION))) {
2667 val = 0xff; 2667 val = 0xff;
2668 } else { 2668 } else {
2669 switch (addr) { 2669 switch (addr) {
2670 case 0x3c0: 2670 case 0x3c0:
2671 - if (s->ar_flip_flop == 0) {  
2672 - val = s->ar_index; 2671 + if (s->vga.ar_flip_flop == 0) {
  2672 + val = s->vga.ar_index;
2673 } else { 2673 } else {
2674 val = 0; 2674 val = 0;
2675 } 2675 }
2676 break; 2676 break;
2677 case 0x3c1: 2677 case 0x3c1:
2678 - index = s->ar_index & 0x1f; 2678 + index = s->vga.ar_index & 0x1f;
2679 if (index < 21) 2679 if (index < 21)
2680 - val = s->ar[index]; 2680 + val = s->vga.ar[index];
2681 else 2681 else
2682 val = 0; 2682 val = 0;
2683 break; 2683 break;
2684 case 0x3c2: 2684 case 0x3c2:
2685 - val = s->st00; 2685 + val = s->vga.st00;
2686 break; 2686 break;
2687 case 0x3c4: 2687 case 0x3c4:
2688 - val = s->sr_index; 2688 + val = s->vga.sr_index;
2689 break; 2689 break;
2690 case 0x3c5: 2690 case 0x3c5:
2691 - if (cirrus_hook_read_sr(s, s->sr_index, &val)) 2691 + if (cirrus_hook_read_sr(s, s->vga.sr_index, &val))
2692 break; 2692 break;
2693 - val = s->sr[s->sr_index]; 2693 + val = s->vga.sr[s->vga.sr_index];
2694 #ifdef DEBUG_VGA_REG 2694 #ifdef DEBUG_VGA_REG
2695 - printf("vga: read SR%x = 0x%02x\n", s->sr_index, val); 2695 + printf("vga: read SR%x = 0x%02x\n", s->vga.sr_index, val);
2696 #endif 2696 #endif
2697 break; 2697 break;
2698 case 0x3c6: 2698 case 0x3c6:
2699 cirrus_read_hidden_dac(s, &val); 2699 cirrus_read_hidden_dac(s, &val);
2700 break; 2700 break;
2701 case 0x3c7: 2701 case 0x3c7:
2702 - val = s->dac_state; 2702 + val = s->vga.dac_state;
2703 break; 2703 break;
2704 case 0x3c8: 2704 case 0x3c8:
2705 - val = s->dac_write_index; 2705 + val = s->vga.dac_write_index;
2706 s->cirrus_hidden_dac_lockindex = 0; 2706 s->cirrus_hidden_dac_lockindex = 0;
2707 break; 2707 break;
2708 case 0x3c9: 2708 case 0x3c9:
2709 if (cirrus_hook_read_palette(s, &val)) 2709 if (cirrus_hook_read_palette(s, &val))
2710 break; 2710 break;
2711 - val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];  
2712 - if (++s->dac_sub_index == 3) {  
2713 - s->dac_sub_index = 0;  
2714 - s->dac_read_index++; 2711 + val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
  2712 + if (++s->vga.dac_sub_index == 3) {
  2713 + s->vga.dac_sub_index = 0;
  2714 + s->vga.dac_read_index++;
2715 } 2715 }
2716 break; 2716 break;
2717 case 0x3ca: 2717 case 0x3ca:
2718 - val = s->fcr; 2718 + val = s->vga.fcr;
2719 break; 2719 break;
2720 case 0x3cc: 2720 case 0x3cc:
2721 - val = s->msr; 2721 + val = s->vga.msr;
2722 break; 2722 break;
2723 case 0x3ce: 2723 case 0x3ce:
2724 - val = s->gr_index; 2724 + val = s->vga.gr_index;
2725 break; 2725 break;
2726 case 0x3cf: 2726 case 0x3cf:
2727 - if (cirrus_hook_read_gr(s, s->gr_index, &val)) 2727 + if (cirrus_hook_read_gr(s, s->vga.gr_index, &val))
2728 break; 2728 break;
2729 - val = s->gr[s->gr_index]; 2729 + val = s->vga.gr[s->vga.gr_index];
2730 #ifdef DEBUG_VGA_REG 2730 #ifdef DEBUG_VGA_REG
2731 - printf("vga: read GR%x = 0x%02x\n", s->gr_index, val); 2731 + printf("vga: read GR%x = 0x%02x\n", s->vga.gr_index, val);
2732 #endif 2732 #endif
2733 break; 2733 break;
2734 case 0x3b4: 2734 case 0x3b4:
2735 case 0x3d4: 2735 case 0x3d4:
2736 - val = s->cr_index; 2736 + val = s->vga.cr_index;
2737 break; 2737 break;
2738 case 0x3b5: 2738 case 0x3b5:
2739 case 0x3d5: 2739 case 0x3d5:
2740 - if (cirrus_hook_read_cr(s, s->cr_index, &val)) 2740 + if (cirrus_hook_read_cr(s, s->vga.cr_index, &val))
2741 break; 2741 break;
2742 - val = s->cr[s->cr_index]; 2742 + val = s->vga.cr[s->vga.cr_index];
2743 #ifdef DEBUG_VGA_REG 2743 #ifdef DEBUG_VGA_REG
2744 - printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); 2744 + printf("vga: read CR%x = 0x%02x\n", s->vga.cr_index, val);
2745 #endif 2745 #endif
2746 break; 2746 break;
2747 case 0x3ba: 2747 case 0x3ba:
2748 case 0x3da: 2748 case 0x3da:
2749 /* just toggle to fool polling */ 2749 /* just toggle to fool polling */
2750 - val = s->st01 = s->retrace((VGAState *) s);  
2751 - s->ar_flip_flop = 0; 2750 + val = s->vga.st01 = s->vga.retrace(&s->vga);
  2751 + s->vga.ar_flip_flop = 0;
2752 break; 2752 break;
2753 default: 2753 default:
2754 val = 0x00; 2754 val = 0x00;
@@ -2767,9 +2767,9 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) @@ -2767,9 +2767,9 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2767 int index; 2767 int index;
2768 2768
2769 /* check port range access depending on color/monochrome mode */ 2769 /* check port range access depending on color/monochrome mode */
2770 - if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) 2770 + if ((addr >= 0x3b0 && addr <= 0x3bf && (s->vga.msr & MSR_COLOR_EMULATION))
2771 || (addr >= 0x3d0 && addr <= 0x3df 2771 || (addr >= 0x3d0 && addr <= 0x3df
2772 - && !(s->msr & MSR_COLOR_EMULATION))) 2772 + && !(s->vga.msr & MSR_COLOR_EMULATION)))
2773 return; 2773 return;
2774 2774
2775 #ifdef DEBUG_VGA 2775 #ifdef DEBUG_VGA
@@ -2778,120 +2778,120 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) @@ -2778,120 +2778,120 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2778 2778
2779 switch (addr) { 2779 switch (addr) {
2780 case 0x3c0: 2780 case 0x3c0:
2781 - if (s->ar_flip_flop == 0) { 2781 + if (s->vga.ar_flip_flop == 0) {
2782 val &= 0x3f; 2782 val &= 0x3f;
2783 - s->ar_index = val; 2783 + s->vga.ar_index = val;
2784 } else { 2784 } else {
2785 - index = s->ar_index & 0x1f; 2785 + index = s->vga.ar_index & 0x1f;
2786 switch (index) { 2786 switch (index) {
2787 case 0x00 ... 0x0f: 2787 case 0x00 ... 0x0f:
2788 - s->ar[index] = val & 0x3f; 2788 + s->vga.ar[index] = val & 0x3f;
2789 break; 2789 break;
2790 case 0x10: 2790 case 0x10:
2791 - s->ar[index] = val & ~0x10; 2791 + s->vga.ar[index] = val & ~0x10;
2792 break; 2792 break;
2793 case 0x11: 2793 case 0x11:
2794 - s->ar[index] = val; 2794 + s->vga.ar[index] = val;
2795 break; 2795 break;
2796 case 0x12: 2796 case 0x12:
2797 - s->ar[index] = val & ~0xc0; 2797 + s->vga.ar[index] = val & ~0xc0;
2798 break; 2798 break;
2799 case 0x13: 2799 case 0x13:
2800 - s->ar[index] = val & ~0xf0; 2800 + s->vga.ar[index] = val & ~0xf0;
2801 break; 2801 break;
2802 case 0x14: 2802 case 0x14:
2803 - s->ar[index] = val & ~0xf0; 2803 + s->vga.ar[index] = val & ~0xf0;
2804 break; 2804 break;
2805 default: 2805 default:
2806 break; 2806 break;
2807 } 2807 }
2808 } 2808 }
2809 - s->ar_flip_flop ^= 1; 2809 + s->vga.ar_flip_flop ^= 1;
2810 break; 2810 break;
2811 case 0x3c2: 2811 case 0x3c2:
2812 - s->msr = val & ~0x10;  
2813 - s->update_retrace_info((VGAState *) s); 2812 + s->vga.msr = val & ~0x10;
  2813 + s->vga.update_retrace_info(&s->vga);
2814 break; 2814 break;
2815 case 0x3c4: 2815 case 0x3c4:
2816 - s->sr_index = val; 2816 + s->vga.sr_index = val;
2817 break; 2817 break;
2818 case 0x3c5: 2818 case 0x3c5:
2819 - if (cirrus_hook_write_sr(s, s->sr_index, val)) 2819 + if (cirrus_hook_write_sr(s, s->vga.sr_index, val))
2820 break; 2820 break;
2821 #ifdef DEBUG_VGA_REG 2821 #ifdef DEBUG_VGA_REG
2822 - printf("vga: write SR%x = 0x%02x\n", s->sr_index, val); 2822 + printf("vga: write SR%x = 0x%02x\n", s->vga.sr_index, val);
2823 #endif 2823 #endif
2824 - s->sr[s->sr_index] = val & sr_mask[s->sr_index];  
2825 - if (s->sr_index == 1) s->update_retrace_info((VGAState *) s); 2824 + s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
  2825 + if (s->vga.sr_index == 1) s->vga.update_retrace_info(&s->vga);
2826 break; 2826 break;
2827 case 0x3c6: 2827 case 0x3c6:
2828 cirrus_write_hidden_dac(s, val); 2828 cirrus_write_hidden_dac(s, val);
2829 break; 2829 break;
2830 case 0x3c7: 2830 case 0x3c7:
2831 - s->dac_read_index = val;  
2832 - s->dac_sub_index = 0;  
2833 - s->dac_state = 3; 2831 + s->vga.dac_read_index = val;
  2832 + s->vga.dac_sub_index = 0;
  2833 + s->vga.dac_state = 3;
2834 break; 2834 break;
2835 case 0x3c8: 2835 case 0x3c8:
2836 - s->dac_write_index = val;  
2837 - s->dac_sub_index = 0;  
2838 - s->dac_state = 0; 2836 + s->vga.dac_write_index = val;
  2837 + s->vga.dac_sub_index = 0;
  2838 + s->vga.dac_state = 0;
2839 break; 2839 break;
2840 case 0x3c9: 2840 case 0x3c9:
2841 if (cirrus_hook_write_palette(s, val)) 2841 if (cirrus_hook_write_palette(s, val))
2842 break; 2842 break;
2843 - s->dac_cache[s->dac_sub_index] = val;  
2844 - if (++s->dac_sub_index == 3) {  
2845 - memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);  
2846 - s->dac_sub_index = 0;  
2847 - s->dac_write_index++; 2843 + s->vga.dac_cache[s->vga.dac_sub_index] = val;
  2844 + if (++s->vga.dac_sub_index == 3) {
  2845 + memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
  2846 + s->vga.dac_sub_index = 0;
  2847 + s->vga.dac_write_index++;
2848 } 2848 }
2849 break; 2849 break;
2850 case 0x3ce: 2850 case 0x3ce:
2851 - s->gr_index = val; 2851 + s->vga.gr_index = val;
2852 break; 2852 break;
2853 case 0x3cf: 2853 case 0x3cf:
2854 - if (cirrus_hook_write_gr(s, s->gr_index, val)) 2854 + if (cirrus_hook_write_gr(s, s->vga.gr_index, val))
2855 break; 2855 break;
2856 #ifdef DEBUG_VGA_REG 2856 #ifdef DEBUG_VGA_REG
2857 - printf("vga: write GR%x = 0x%02x\n", s->gr_index, val); 2857 + printf("vga: write GR%x = 0x%02x\n", s->vga.gr_index, val);
2858 #endif 2858 #endif
2859 - s->gr[s->gr_index] = val & gr_mask[s->gr_index]; 2859 + s->vga.gr[s->vga.gr_index] = val & gr_mask[s->vga.gr_index];
2860 break; 2860 break;
2861 case 0x3b4: 2861 case 0x3b4:
2862 case 0x3d4: 2862 case 0x3d4:
2863 - s->cr_index = val; 2863 + s->vga.cr_index = val;
2864 break; 2864 break;
2865 case 0x3b5: 2865 case 0x3b5:
2866 case 0x3d5: 2866 case 0x3d5:
2867 - if (cirrus_hook_write_cr(s, s->cr_index, val)) 2867 + if (cirrus_hook_write_cr(s, s->vga.cr_index, val))
2868 break; 2868 break;
2869 #ifdef DEBUG_VGA_REG 2869 #ifdef DEBUG_VGA_REG
2870 - printf("vga: write CR%x = 0x%02x\n", s->cr_index, val); 2870 + printf("vga: write CR%x = 0x%02x\n", s->vga.cr_index, val);
2871 #endif 2871 #endif
2872 /* handle CR0-7 protection */ 2872 /* handle CR0-7 protection */
2873 - if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) { 2873 + if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
2874 /* can always write bit 4 of CR7 */ 2874 /* can always write bit 4 of CR7 */
2875 - if (s->cr_index == 7)  
2876 - s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10); 2875 + if (s->vga.cr_index == 7)
  2876 + s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (val & 0x10);
2877 return; 2877 return;
2878 } 2878 }
2879 - switch (s->cr_index) { 2879 + switch (s->vga.cr_index) {
2880 case 0x01: /* horizontal display end */ 2880 case 0x01: /* horizontal display end */
2881 case 0x07: 2881 case 0x07:
2882 case 0x09: 2882 case 0x09:
2883 case 0x0c: 2883 case 0x0c:
2884 case 0x0d: 2884 case 0x0d:
2885 case 0x12: /* vertical display end */ 2885 case 0x12: /* vertical display end */
2886 - s->cr[s->cr_index] = val; 2886 + s->vga.cr[s->vga.cr_index] = val;
2887 break; 2887 break;
2888 2888
2889 default: 2889 default:
2890 - s->cr[s->cr_index] = val; 2890 + s->vga.cr[s->vga.cr_index] = val;
2891 break; 2891 break;
2892 } 2892 }
2893 2893
2894 - switch(s->cr_index) { 2894 + switch(s->vga.cr_index) {
2895 case 0x00: 2895 case 0x00:
2896 case 0x04: 2896 case 0x04:
2897 case 0x05: 2897 case 0x05:
@@ -2899,13 +2899,13 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) @@ -2899,13 +2899,13 @@ static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2899 case 0x07: 2899 case 0x07:
2900 case 0x11: 2900 case 0x11:
2901 case 0x17: 2901 case 0x17:
2902 - s->update_retrace_info((VGAState *) s); 2902 + s->vga.update_retrace_info(&s->vga);
2903 break; 2903 break;
2904 } 2904 }
2905 break; 2905 break;
2906 case 0x3ba: 2906 case 0x3ba:
2907 case 0x3da: 2907 case 0x3da:
2908 - s->fcr = val & 0x10; 2908 + s->vga.fcr = val & 0x10;
2909 break; 2909 break;
2910 } 2910 }
2911 } 2911 }
@@ -3020,34 +3020,34 @@ static void cirrus_vga_save(QEMUFile *f, void *opaque) @@ -3020,34 +3020,34 @@ static void cirrus_vga_save(QEMUFile *f, void *opaque)
3020 { 3020 {
3021 CirrusVGAState *s = opaque; 3021 CirrusVGAState *s = opaque;
3022 3022
3023 - if (s->pci_dev)  
3024 - pci_device_save(s->pci_dev, f); 3023 + if (s->vga.pci_dev)
  3024 + pci_device_save(s->vga.pci_dev, f);
3025 3025
3026 - qemu_put_be32s(f, &s->latch);  
3027 - qemu_put_8s(f, &s->sr_index);  
3028 - qemu_put_buffer(f, s->sr, 256);  
3029 - qemu_put_8s(f, &s->gr_index); 3026 + qemu_put_be32s(f, &s->vga.latch);
  3027 + qemu_put_8s(f, &s->vga.sr_index);
  3028 + qemu_put_buffer(f, s->vga.sr, 256);
  3029 + qemu_put_8s(f, &s->vga.gr_index);
3030 qemu_put_8s(f, &s->cirrus_shadow_gr0); 3030 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3031 qemu_put_8s(f, &s->cirrus_shadow_gr1); 3031 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3032 - qemu_put_buffer(f, s->gr + 2, 254);  
3033 - qemu_put_8s(f, &s->ar_index);  
3034 - qemu_put_buffer(f, s->ar, 21);  
3035 - qemu_put_be32(f, s->ar_flip_flop);  
3036 - qemu_put_8s(f, &s->cr_index);  
3037 - qemu_put_buffer(f, s->cr, 256);  
3038 - qemu_put_8s(f, &s->msr);  
3039 - qemu_put_8s(f, &s->fcr);  
3040 - qemu_put_8s(f, &s->st00);  
3041 - qemu_put_8s(f, &s->st01);  
3042 -  
3043 - qemu_put_8s(f, &s->dac_state);  
3044 - qemu_put_8s(f, &s->dac_sub_index);  
3045 - qemu_put_8s(f, &s->dac_read_index);  
3046 - qemu_put_8s(f, &s->dac_write_index);  
3047 - qemu_put_buffer(f, s->dac_cache, 3);  
3048 - qemu_put_buffer(f, s->palette, 768);  
3049 -  
3050 - qemu_put_be32(f, s->bank_offset); 3032 + qemu_put_buffer(f, s->vga.gr + 2, 254);
  3033 + qemu_put_8s(f, &s->vga.ar_index);
  3034 + qemu_put_buffer(f, s->vga.ar, 21);
  3035 + qemu_put_be32(f, s->vga.ar_flip_flop);
  3036 + qemu_put_8s(f, &s->vga.cr_index);
  3037 + qemu_put_buffer(f, s->vga.cr, 256);
  3038 + qemu_put_8s(f, &s->vga.msr);
  3039 + qemu_put_8s(f, &s->vga.fcr);
  3040 + qemu_put_8s(f, &s->vga.st00);
  3041 + qemu_put_8s(f, &s->vga.st01);
  3042 +
  3043 + qemu_put_8s(f, &s->vga.dac_state);
  3044 + qemu_put_8s(f, &s->vga.dac_sub_index);
  3045 + qemu_put_8s(f, &s->vga.dac_read_index);
  3046 + qemu_put_8s(f, &s->vga.dac_write_index);
  3047 + qemu_put_buffer(f, s->vga.dac_cache, 3);
  3048 + qemu_put_buffer(f, s->vga.palette, 768);
  3049 +
  3050 + qemu_put_be32(f, s->vga.bank_offset);
3051 3051
3052 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex); 3052 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3053 qemu_put_8s(f, &s->cirrus_hidden_dac_data); 3053 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
@@ -3066,39 +3066,39 @@ static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id) @@ -3066,39 +3066,39 @@ static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3066 if (version_id > 2) 3066 if (version_id > 2)
3067 return -EINVAL; 3067 return -EINVAL;
3068 3068
3069 - if (s->pci_dev && version_id >= 2) {  
3070 - ret = pci_device_load(s->pci_dev, f); 3069 + if (s->vga.pci_dev && version_id >= 2) {
  3070 + ret = pci_device_load(s->vga.pci_dev, f);
3071 if (ret < 0) 3071 if (ret < 0)
3072 return ret; 3072 return ret;
3073 } 3073 }
3074 3074
3075 - qemu_get_be32s(f, &s->latch);  
3076 - qemu_get_8s(f, &s->sr_index);  
3077 - qemu_get_buffer(f, s->sr, 256);  
3078 - qemu_get_8s(f, &s->gr_index); 3075 + qemu_get_be32s(f, &s->vga.latch);
  3076 + qemu_get_8s(f, &s->vga.sr_index);
  3077 + qemu_get_buffer(f, s->vga.sr, 256);
  3078 + qemu_get_8s(f, &s->vga.gr_index);
3079 qemu_get_8s(f, &s->cirrus_shadow_gr0); 3079 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3080 qemu_get_8s(f, &s->cirrus_shadow_gr1); 3080 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3081 - s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;  
3082 - s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;  
3083 - qemu_get_buffer(f, s->gr + 2, 254);  
3084 - qemu_get_8s(f, &s->ar_index);  
3085 - qemu_get_buffer(f, s->ar, 21);  
3086 - s->ar_flip_flop=qemu_get_be32(f);  
3087 - qemu_get_8s(f, &s->cr_index);  
3088 - qemu_get_buffer(f, s->cr, 256);  
3089 - qemu_get_8s(f, &s->msr);  
3090 - qemu_get_8s(f, &s->fcr);  
3091 - qemu_get_8s(f, &s->st00);  
3092 - qemu_get_8s(f, &s->st01);  
3093 -  
3094 - qemu_get_8s(f, &s->dac_state);  
3095 - qemu_get_8s(f, &s->dac_sub_index);  
3096 - qemu_get_8s(f, &s->dac_read_index);  
3097 - qemu_get_8s(f, &s->dac_write_index);  
3098 - qemu_get_buffer(f, s->dac_cache, 3);  
3099 - qemu_get_buffer(f, s->palette, 768);  
3100 -  
3101 - s->bank_offset=qemu_get_be32(f); 3081 + s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
  3082 + s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
  3083 + qemu_get_buffer(f, s->vga.gr + 2, 254);
  3084 + qemu_get_8s(f, &s->vga.ar_index);
  3085 + qemu_get_buffer(f, s->vga.ar, 21);
  3086 + s->vga.ar_flip_flop=qemu_get_be32(f);
  3087 + qemu_get_8s(f, &s->vga.cr_index);
  3088 + qemu_get_buffer(f, s->vga.cr, 256);
  3089 + qemu_get_8s(f, &s->vga.msr);
  3090 + qemu_get_8s(f, &s->vga.fcr);
  3091 + qemu_get_8s(f, &s->vga.st00);
  3092 + qemu_get_8s(f, &s->vga.st01);
  3093 +
  3094 + qemu_get_8s(f, &s->vga.dac_state);
  3095 + qemu_get_8s(f, &s->vga.dac_sub_index);
  3096 + qemu_get_8s(f, &s->vga.dac_read_index);
  3097 + qemu_get_8s(f, &s->vga.dac_write_index);
  3098 + qemu_get_buffer(f, s->vga.dac_cache, 3);
  3099 + qemu_get_buffer(f, s->vga.palette, 768);
  3100 +
  3101 + s->vga.bank_offset = qemu_get_be32(f);
3102 3102
3103 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex); 3103 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3104 qemu_get_8s(f, &s->cirrus_hidden_dac_data); 3104 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
@@ -3108,7 +3108,7 @@ static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id) @@ -3108,7 +3108,7 @@ static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3108 3108
3109 cirrus_update_memory_access(s); 3109 cirrus_update_memory_access(s);
3110 /* force refresh */ 3110 /* force refresh */
3111 - s->graphic_mode = -1; 3111 + s->vga.graphic_mode = -1;
3112 cirrus_update_bank_ptr(s, 0); 3112 cirrus_update_bank_ptr(s, 0);
3113 cirrus_update_bank_ptr(s, 1); 3113 cirrus_update_bank_ptr(s, 1);
3114 return 0; 3114 return 0;
@@ -3126,25 +3126,25 @@ static void cirrus_reset(void *opaque) @@ -3126,25 +3126,25 @@ static void cirrus_reset(void *opaque)
3126 3126
3127 vga_reset(s); 3127 vga_reset(s);
3128 unmap_linear_vram(s); 3128 unmap_linear_vram(s);
3129 - s->sr[0x06] = 0x0f; 3129 + s->vga.sr[0x06] = 0x0f;
3130 if (s->device_id == CIRRUS_ID_CLGD5446) { 3130 if (s->device_id == CIRRUS_ID_CLGD5446) {
3131 /* 4MB 64 bit memory config, always PCI */ 3131 /* 4MB 64 bit memory config, always PCI */
3132 - s->sr[0x1F] = 0x2d; // MemClock  
3133 - s->gr[0x18] = 0x0f; // fastest memory configuration  
3134 - s->sr[0x0f] = 0x98;  
3135 - s->sr[0x17] = 0x20;  
3136 - s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ 3132 + s->vga.sr[0x1F] = 0x2d; // MemClock
  3133 + s->vga.gr[0x18] = 0x0f; // fastest memory configuration
  3134 + s->vga.sr[0x0f] = 0x98;
  3135 + s->vga.sr[0x17] = 0x20;
  3136 + s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3137 } else { 3137 } else {
3138 - s->sr[0x1F] = 0x22; // MemClock  
3139 - s->sr[0x0F] = CIRRUS_MEMSIZE_2M;  
3140 - s->sr[0x17] = s->bustype;  
3141 - s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ 3138 + s->vga.sr[0x1F] = 0x22; // MemClock
  3139 + s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
  3140 + s->vga.sr[0x17] = s->bustype;
  3141 + s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3142 } 3142 }
3143 - s->cr[0x27] = s->device_id; 3143 + s->vga.cr[0x27] = s->device_id;
3144 3144
3145 /* Win2K seems to assume that the pattern buffer is at 0xff 3145 /* Win2K seems to assume that the pattern buffer is at 0xff
3146 initially ! */ 3146 initially ! */
3147 - memset(s->vram_ptr, 0xff, s->real_vram_size); 3147 + memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
3148 3148
3149 s->cirrus_hidden_dac_lockindex = 5; 3149 s->cirrus_hidden_dac_lockindex = 5;
3150 s->cirrus_hidden_dac_data = 0; 3150 s->cirrus_hidden_dac_data = 0;
@@ -3196,10 +3196,10 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) @@ -3196,10 +3196,10 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3196 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); 3196 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3197 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); 3197 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3198 3198
3199 - s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,  
3200 - cirrus_vga_mem_write, s); 3199 + s->vga.vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
  3200 + cirrus_vga_mem_write, s);
3201 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, 3201 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3202 - s->vga_io_memory); 3202 + s->vga.vga_io_memory);
3203 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); 3203 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3204 3204
3205 /* I/O handler for LFB */ 3205 /* I/O handler for LFB */
@@ -3218,15 +3218,15 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) @@ -3218,15 +3218,15 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3218 s->real_vram_size = 3218 s->real_vram_size =
3219 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; 3219 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3220 3220
3221 - /* XXX: s->vram_size must be a power of two */ 3221 + /* XXX: s->vga.vram_size must be a power of two */
3222 s->cirrus_addr_mask = s->real_vram_size - 1; 3222 s->cirrus_addr_mask = s->real_vram_size - 1;
3223 s->linear_mmio_mask = s->real_vram_size - 256; 3223 s->linear_mmio_mask = s->real_vram_size - 256;
3224 3224
3225 - s->get_bpp = cirrus_get_bpp;  
3226 - s->get_offsets = cirrus_get_offsets;  
3227 - s->get_resolution = cirrus_get_resolution;  
3228 - s->cursor_invalidate = cirrus_cursor_invalidate;  
3229 - s->cursor_draw_line = cirrus_cursor_draw_line; 3225 + s->vga.get_bpp = cirrus_get_bpp;
  3226 + s->vga.get_offsets = cirrus_get_offsets;
  3227 + s->vga.get_resolution = cirrus_get_resolution;
  3228 + s->vga.cursor_invalidate = cirrus_cursor_invalidate;
  3229 + s->vga.cursor_draw_line = cirrus_cursor_draw_line;
3230 3230
3231 qemu_register_reset(cirrus_reset, s); 3231 qemu_register_reset(cirrus_reset, s);
3232 cirrus_reset(s); 3232 cirrus_reset(s);
@@ -3245,10 +3245,11 @@ void isa_cirrus_vga_init(int vga_ram_size) @@ -3245,10 +3245,11 @@ void isa_cirrus_vga_init(int vga_ram_size)
3245 3245
3246 s = qemu_mallocz(sizeof(CirrusVGAState)); 3246 s = qemu_mallocz(sizeof(CirrusVGAState));
3247 3247
3248 - vga_common_init((VGAState *)s, vga_ram_size); 3248 + vga_common_init(&s->vga, vga_ram_size);
3249 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0); 3249 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3250 - s->ds = graphic_console_init(s->update, s->invalidate,  
3251 - s->screen_dump, s->text_update, s); 3250 + s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
  3251 + s->vga.screen_dump, s->vga.text_update,
  3252 + &s->vga);
3252 /* XXX ISA-LFB support */ 3253 /* XXX ISA-LFB support */
3253 } 3254 }
3254 3255
@@ -3264,19 +3265,19 @@ static void cirrus_pci_lfb_map(PCIDevice *d, int region_num, @@ -3264,19 +3265,19 @@ static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3264 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga; 3265 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3265 3266
3266 /* XXX: add byte swapping apertures */ 3267 /* XXX: add byte swapping apertures */
3267 - cpu_register_physical_memory(addr, s->vram_size, 3268 + cpu_register_physical_memory(addr, s->vga.vram_size,
3268 s->cirrus_linear_io_addr); 3269 s->cirrus_linear_io_addr);
3269 cpu_register_physical_memory(addr + 0x1000000, 0x400000, 3270 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3270 s->cirrus_linear_bitblt_io_addr); 3271 s->cirrus_linear_bitblt_io_addr);
3271 3272
3272 - s->map_addr = s->map_end = 0;  
3273 - s->lfb_addr = addr & TARGET_PAGE_MASK;  
3274 - s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 3273 + s->vga.map_addr = s->vga.map_end = 0;
  3274 + s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
  3275 + s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3275 /* account for overflow */ 3276 /* account for overflow */
3276 - if (s->lfb_end < addr + VGA_RAM_SIZE)  
3277 - s->lfb_end = addr + VGA_RAM_SIZE; 3277 + if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
  3278 + s->vga.lfb_end = addr + VGA_RAM_SIZE;
3278 3279
3279 - vga_dirty_log_start((VGAState *)s); 3280 + vga_dirty_log_start(&s->vga);
3280 } 3281 }
3281 3282
3282 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num, 3283 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
@@ -3295,8 +3296,8 @@ static void pci_cirrus_write_config(PCIDevice *d, @@ -3295,8 +3296,8 @@ static void pci_cirrus_write_config(PCIDevice *d,
3295 CirrusVGAState *s = &pvs->cirrus_vga; 3296 CirrusVGAState *s = &pvs->cirrus_vga;
3296 3297
3297 pci_default_write_config(d, address, val, len); 3298 pci_default_write_config(d, address, val, len);
3298 - if (s->map_addr && pvs->dev.io_regions[0].addr == -1)  
3299 - s->map_addr = 0; 3299 + if (s->vga.map_addr && pvs->dev.io_regions[0].addr == -1)
  3300 + s->vga.map_addr = 0;
3300 cirrus_update_memory_access(s); 3301 cirrus_update_memory_access(s);
3301 } 3302 }
3302 3303
@@ -3322,18 +3323,19 @@ void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size) @@ -3322,18 +3323,19 @@ void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size)
3322 3323
3323 /* setup VGA */ 3324 /* setup VGA */
3324 s = &d->cirrus_vga; 3325 s = &d->cirrus_vga;
3325 - vga_common_init((VGAState *)s, vga_ram_size); 3326 + vga_common_init(&s->vga, vga_ram_size);
3326 cirrus_init_common(s, device_id, 1); 3327 cirrus_init_common(s, device_id, 1);
3327 3328
3328 - s->ds = graphic_console_init(s->update, s->invalidate,  
3329 - s->screen_dump, s->text_update, s); 3329 + s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
  3330 + s->vga.screen_dump, s->vga.text_update,
  3331 + &s->vga);
3330 3332
3331 - s->pci_dev = (PCIDevice *)d; 3333 + s->vga.pci_dev = (PCIDevice *)d;
3332 3334
3333 /* setup memory space */ 3335 /* setup memory space */
3334 /* memory #0 LFB */ 3336 /* memory #0 LFB */
3335 /* memory #1 memory-mapped I/O */ 3337 /* memory #1 memory-mapped I/O */
3336 - /* XXX: s->vram_size must be a power of two */ 3338 + /* XXX: s->vga.vram_size must be a power of two */
3337 pci_register_io_region((PCIDevice *)d, 0, 0x2000000, 3339 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3338 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map); 3340 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3339 if (device_id == CIRRUS_ID_CLGD5446) { 3341 if (device_id == CIRRUS_ID_CLGD5446) {
hw/cirrus_vga_rop.h
  View file @4e12cd9
@@ -82,7 +82,7 @@ glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_8)(CirrusVGAState *s, @@ -82,7 +82,7 @@ glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_8)(CirrusVGAState *s,
82 for (x = 0; x < bltwidth; x++) { 82 for (x = 0; x < bltwidth; x++) {
83 p = *dst; 83 p = *dst;
84 ROP_OP(p, *src); 84 ROP_OP(p, *src);
85 - if (p != s->gr[0x34]) *dst = p; 85 + if (p != s->vga.gr[0x34]) *dst = p;
86 dst++; 86 dst++;
87 src++; 87 src++;
88 } 88 }
@@ -105,7 +105,7 @@ glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_8)(CirrusVGAState *s, @@ -105,7 +105,7 @@ glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_8)(CirrusVGAState *s,
105 for (x = 0; x < bltwidth; x++) { 105 for (x = 0; x < bltwidth; x++) {
106 p = *dst; 106 p = *dst;
107 ROP_OP(p, *src); 107 ROP_OP(p, *src);
108 - if (p != s->gr[0x34]) *dst = p; 108 + if (p != s->vga.gr[0x34]) *dst = p;
109 dst--; 109 dst--;
110 src--; 110 src--;
111 } 111 }
@@ -130,7 +130,7 @@ glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_16)(CirrusVGAState *s, @@ -130,7 +130,7 @@ glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_16)(CirrusVGAState *s,
130 p2 = *(dst+1); 130 p2 = *(dst+1);
131 ROP_OP(p1, *src); 131 ROP_OP(p1, *src);
132 ROP_OP(p2, *(src+1)); 132 ROP_OP(p2, *(src+1));
133 - if ((p1 != s->gr[0x34]) || (p2 != s->gr[0x35])) { 133 + if ((p1 != s->vga.gr[0x34]) || (p2 != s->vga.gr[0x35])) {
134 *dst = p1; 134 *dst = p1;
135 *(dst+1) = p2; 135 *(dst+1) = p2;
136 } 136 }
@@ -158,7 +158,7 @@ glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_16)(CirrusVGAState *s, @@ -158,7 +158,7 @@ glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_16)(CirrusVGAState *s,
158 p2 = *dst; 158 p2 = *dst;
159 ROP_OP(p1, *(src-1)); 159 ROP_OP(p1, *(src-1));
160 ROP_OP(p2, *src); 160 ROP_OP(p2, *src);
161 - if ((p1 != s->gr[0x34]) || (p2 != s->gr[0x35])) { 161 + if ((p1 != s->vga.gr[0x34]) || (p2 != s->vga.gr[0x35])) {
162 *(dst-1) = p1; 162 *(dst-1) = p1;
163 *dst = p2; 163 *dst = p2;
164 } 164 }
hw/cirrus_vga_rop2.h
  View file @4e12cd9
@@ -48,9 +48,9 @@ glue(glue(glue(cirrus_patternfill_, ROP_NAME), _),DEPTH) @@ -48,9 +48,9 @@ glue(glue(glue(cirrus_patternfill_, ROP_NAME), _),DEPTH)
48 unsigned int col; 48 unsigned int col;
49 const uint8_t *src1; 49 const uint8_t *src1;
50 #if DEPTH == 24 50 #if DEPTH == 24
51 - int skipleft = s->gr[0x2f] & 0x1f; 51 + int skipleft = s->vga.gr[0x2f] & 0x1f;
52 #else 52 #else
53 - int skipleft = (s->gr[0x2f] & 0x07) * (DEPTH / 8); 53 + int skipleft = (s->vga.gr[0x2f] & 0x07) * (DEPTH / 8);
54 #endif 54 #endif
55 55
56 #if DEPTH == 8 56 #if DEPTH == 8
@@ -105,10 +105,10 @@ glue(glue(glue(cirrus_colorexpand_transp_, ROP_NAME), _),DEPTH) @@ -105,10 +105,10 @@ glue(glue(glue(cirrus_colorexpand_transp_, ROP_NAME), _),DEPTH)
105 unsigned bitmask; 105 unsigned bitmask;
106 unsigned index; 106 unsigned index;
107 #if DEPTH == 24 107 #if DEPTH == 24
108 - int dstskipleft = s->gr[0x2f] & 0x1f; 108 + int dstskipleft = s->vga.gr[0x2f] & 0x1f;
109 int srcskipleft = dstskipleft / 3; 109 int srcskipleft = dstskipleft / 3;
110 #else 110 #else
111 - int srcskipleft = s->gr[0x2f] & 0x07; 111 + int srcskipleft = s->vga.gr[0x2f] & 0x07;
112 int dstskipleft = srcskipleft * (DEPTH / 8); 112 int dstskipleft = srcskipleft * (DEPTH / 8);
113 #endif 113 #endif
114 114
@@ -153,7 +153,7 @@ glue(glue(glue(cirrus_colorexpand_, ROP_NAME), _),DEPTH) @@ -153,7 +153,7 @@ glue(glue(glue(cirrus_colorexpand_, ROP_NAME), _),DEPTH)
153 unsigned bits; 153 unsigned bits;
154 unsigned int col; 154 unsigned int col;
155 unsigned bitmask; 155 unsigned bitmask;
156 - int srcskipleft = s->gr[0x2f] & 0x07; 156 + int srcskipleft = s->vga.gr[0x2f] & 0x07;
157 int dstskipleft = srcskipleft * (DEPTH / 8); 157 int dstskipleft = srcskipleft * (DEPTH / 8);
158 158
159 colors[0] = s->cirrus_blt_bgcol; 159 colors[0] = s->cirrus_blt_bgcol;
@@ -188,10 +188,10 @@ glue(glue(glue(cirrus_colorexpand_pattern_transp_, ROP_NAME), _),DEPTH) @@ -188,10 +188,10 @@ glue(glue(glue(cirrus_colorexpand_pattern_transp_, ROP_NAME), _),DEPTH)
188 unsigned int bits, bits_xor; 188 unsigned int bits, bits_xor;
189 unsigned int col; 189 unsigned int col;
190 #if DEPTH == 24 190 #if DEPTH == 24
191 - int dstskipleft = s->gr[0x2f] & 0x1f; 191 + int dstskipleft = s->vga.gr[0x2f] & 0x1f;
192 int srcskipleft = dstskipleft / 3; 192 int srcskipleft = dstskipleft / 3;
193 #else 193 #else
194 - int srcskipleft = s->gr[0x2f] & 0x07; 194 + int srcskipleft = s->vga.gr[0x2f] & 0x07;
195 int dstskipleft = srcskipleft * (DEPTH / 8); 195 int dstskipleft = srcskipleft * (DEPTH / 8);
196 #endif 196 #endif
197 197
@@ -232,7 +232,7 @@ glue(glue(glue(cirrus_colorexpand_pattern_, ROP_NAME), _),DEPTH) @@ -232,7 +232,7 @@ glue(glue(glue(cirrus_colorexpand_pattern_, ROP_NAME), _),DEPTH)
232 int x, y, bitpos, pattern_y; 232 int x, y, bitpos, pattern_y;
233 unsigned int bits; 233 unsigned int bits;
234 unsigned int col; 234 unsigned int col;
235 - int srcskipleft = s->gr[0x2f] & 0x07; 235 + int srcskipleft = s->vga.gr[0x2f] & 0x07;
236 int dstskipleft = srcskipleft * (DEPTH / 8); 236 int dstskipleft = srcskipleft * (DEPTH / 8);
237 237
238 colors[0] = s->cirrus_blt_bgcol; 238 colors[0] = s->cirrus_blt_bgcol;
hw/vga_int.h
  View file @4e12cd9
@@ -94,94 +94,92 @@ union vga_retrace { @@ -94,94 +94,92 @@ union vga_retrace {
94 struct vga_precise_retrace precise; 94 struct vga_precise_retrace precise;
95 }; 95 };
96 96
97 -struct VGAState;  
98 -typedef uint8_t (* vga_retrace_fn)(struct VGAState *s);  
99 -typedef void (* vga_update_retrace_info_fn)(struct VGAState *s);  
100 -  
101 -#define VGA_STATE_COMMON \  
102 - uint8_t *vram_ptr; \  
103 - ram_addr_t vram_offset; \  
104 - unsigned int vram_size; \  
105 - uint32_t lfb_addr; \  
106 - uint32_t lfb_end; \  
107 - uint32_t map_addr; \  
108 - uint32_t map_end; \  
109 - uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */ \  
110 - unsigned long bios_offset; \  
111 - unsigned int bios_size; \  
112 - int it_shift; \  
113 - PCIDevice *pci_dev; \  
114 - uint32_t latch; \  
115 - uint8_t sr_index; \  
116 - uint8_t sr[256]; \  
117 - uint8_t gr_index; \  
118 - uint8_t gr[256]; \  
119 - uint8_t ar_index; \  
120 - uint8_t ar[21]; \  
121 - int ar_flip_flop; \  
122 - uint8_t cr_index; \  
123 - uint8_t cr[256]; /* CRT registers */ \  
124 - uint8_t msr; /* Misc Output Register */ \  
125 - uint8_t fcr; /* Feature Control Register */ \  
126 - uint8_t st00; /* status 0 */ \  
127 - uint8_t st01; /* status 1 */ \  
128 - uint8_t dac_state; \  
129 - uint8_t dac_sub_index; \  
130 - uint8_t dac_read_index; \  
131 - uint8_t dac_write_index; \  
132 - uint8_t dac_cache[3]; /* used when writing */ \  
133 - int dac_8bit; \  
134 - uint8_t palette[768]; \  
135 - int32_t bank_offset; \  
136 - int vga_io_memory; \  
137 - int (*get_bpp)(struct VGAState *s); \  
138 - void (*get_offsets)(struct VGAState *s, \  
139 - uint32_t *pline_offset, \  
140 - uint32_t *pstart_addr, \  
141 - uint32_t *pline_compare); \  
142 - void (*get_resolution)(struct VGAState *s, \  
143 - int *pwidth, \  
144 - int *pheight); \  
145 - VGA_STATE_COMMON_BOCHS_VBE \  
146 - /* display refresh support */ \  
147 - DisplayState *ds; \  
148 - uint32_t font_offsets[2]; \  
149 - int graphic_mode; \  
150 - uint8_t shift_control; \  
151 - uint8_t double_scan; \  
152 - uint32_t line_offset; \  
153 - uint32_t line_compare; \  
154 - uint32_t start_addr; \  
155 - uint32_t plane_updated; \  
156 - uint32_t last_line_offset; \  
157 - uint8_t last_cw, last_ch; \  
158 - uint32_t last_width, last_height; /* in chars or pixels */ \  
159 - uint32_t last_scr_width, last_scr_height; /* in pixels */ \  
160 - uint32_t last_depth; /* in bits */ \  
161 - uint8_t cursor_start, cursor_end; \  
162 - uint32_t cursor_offset; \  
163 - unsigned int (*rgb_to_pixel)(unsigned int r, \  
164 - unsigned int g, unsigned b); \  
165 - vga_hw_update_ptr update; \  
166 - vga_hw_invalidate_ptr invalidate; \  
167 - vga_hw_screen_dump_ptr screen_dump; \  
168 - vga_hw_text_update_ptr text_update; \  
169 - /* hardware mouse cursor support */ \  
170 - uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \  
171 - void (*cursor_invalidate)(struct VGAState *s); \  
172 - void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \  
173 - /* tell for each page if it has been updated since the last time */ \  
174 - uint32_t last_palette[256]; \  
175 - uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */ \  
176 - /* retrace */ \  
177 - vga_retrace_fn retrace; \  
178 - vga_update_retrace_info_fn update_retrace_info; \ 97 +struct VGACommonState;
  98 +typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
  99 +typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
  100 +
  101 +typedef struct VGACommonState {
  102 + uint8_t *vram_ptr;
  103 + ram_addr_t vram_offset;
  104 + unsigned int vram_size;
  105 + uint32_t lfb_addr;
  106 + uint32_t lfb_end;
  107 + uint32_t map_addr;
  108 + uint32_t map_end;
  109 + uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
  110 + unsigned long bios_offset;
  111 + unsigned int bios_size;
  112 + int it_shift;
  113 + PCIDevice *pci_dev;
  114 + uint32_t latch;
  115 + uint8_t sr_index;
  116 + uint8_t sr[256];
  117 + uint8_t gr_index;
  118 + uint8_t gr[256];
  119 + uint8_t ar_index;
  120 + uint8_t ar[21];
  121 + int ar_flip_flop;
  122 + uint8_t cr_index;
  123 + uint8_t cr[256]; /* CRT registers */
  124 + uint8_t msr; /* Misc Output Register */
  125 + uint8_t fcr; /* Feature Control Register */
  126 + uint8_t st00; /* status 0 */
  127 + uint8_t st01; /* status 1 */
  128 + uint8_t dac_state;
  129 + uint8_t dac_sub_index;
  130 + uint8_t dac_read_index;
  131 + uint8_t dac_write_index;
  132 + uint8_t dac_cache[3]; /* used when writing */
  133 + int dac_8bit;
  134 + uint8_t palette[768];
  135 + int32_t bank_offset;
  136 + int vga_io_memory;
  137 + int (*get_bpp)(struct VGACommonState *s);
  138 + void (*get_offsets)(struct VGACommonState *s,
  139 + uint32_t *pline_offset,
  140 + uint32_t *pstart_addr,
  141 + uint32_t *pline_compare);
  142 + void (*get_resolution)(struct VGACommonState *s,
  143 + int *pwidth,
  144 + int *pheight);
  145 + VGA_STATE_COMMON_BOCHS_VBE
  146 + /* display refresh support */
  147 + DisplayState *ds;
  148 + uint32_t font_offsets[2];
  149 + int graphic_mode;
  150 + uint8_t shift_control;
  151 + uint8_t double_scan;
  152 + uint32_t line_offset;
  153 + uint32_t line_compare;
  154 + uint32_t start_addr;
  155 + uint32_t plane_updated;
  156 + uint32_t last_line_offset;
  157 + uint8_t last_cw, last_ch;
  158 + uint32_t last_width, last_height; /* in chars or pixels */
  159 + uint32_t last_scr_width, last_scr_height; /* in pixels */
  160 + uint32_t last_depth; /* in bits */
  161 + uint8_t cursor_start, cursor_end;
  162 + uint32_t cursor_offset;
  163 + unsigned int (*rgb_to_pixel)(unsigned int r,
  164 + unsigned int g, unsigned b);
  165 + vga_hw_update_ptr update;
  166 + vga_hw_invalidate_ptr invalidate;
  167 + vga_hw_screen_dump_ptr screen_dump;
  168 + vga_hw_text_update_ptr text_update;
  169 + /* hardware mouse cursor support */
  170 + uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
  171 + void (*cursor_invalidate)(struct VGACommonState *s);
  172 + void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
  173 + /* tell for each page if it has been updated since the last time */
  174 + uint32_t last_palette[256];
  175 + uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
  176 + /* retrace */
  177 + vga_retrace_fn retrace;
  178 + vga_update_retrace_info_fn update_retrace_info;
179 union vga_retrace retrace_info; 179 union vga_retrace retrace_info;
  180 +} VGACommonState;
180 181
181 -  
182 -typedef struct VGAState {  
183 - VGA_STATE_COMMON  
184 -} VGAState; 182 +typedef VGACommonState VGAState;
185 183
186 static inline int c6_to_8(int v) 184 static inline int c6_to_8(int v)
187 { 185 {
hw/vmware_vga.c
  View file @4e12cd9
@@ -38,7 +38,7 @@ @@ -38,7 +38,7 @@
38 38
39 struct vmsvga_state_s { 39 struct vmsvga_state_s {
40 #ifdef EMBED_STDVGA 40 #ifdef EMBED_STDVGA
41 - VGA_STATE_COMMON 41 + VGACommonState vga;
42 #endif 42 #endif
43 43
44 int width; 44 int width;
@@ -326,23 +326,23 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s, @@ -326,23 +326,23 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
326 bypl = s->bypp * s->width; 326 bypl = s->bypp * s->width;
327 width = s->bypp * w; 327 width = s->bypp * w;
328 start = s->bypp * x + bypl * y; 328 start = s->bypp * x + bypl * y;
329 - src = s->vram_ptr + start;  
330 - dst = ds_get_data(s->ds) + start; 329 + src = s->vga.vram_ptr + start;
  330 + dst = ds_get_data(s->vga.ds) + start;
331 331
332 for (; line > 0; line --, src += bypl, dst += bypl) 332 for (; line > 0; line --, src += bypl, dst += bypl)
333 memcpy(dst, src, width); 333 memcpy(dst, src, width);
334 #endif 334 #endif
335 335
336 - dpy_update(s->ds, x, y, w, h); 336 + dpy_update(s->vga.ds, x, y, w, h);
337 } 337 }
338 338
339 static inline void vmsvga_update_screen(struct vmsvga_state_s *s) 339 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
340 { 340 {
341 #ifndef DIRECT_VRAM 341 #ifndef DIRECT_VRAM
342 - memcpy(ds_get_data(s->ds), s->vram_ptr, s->bypp * s->width * s->height); 342 + memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
343 #endif 343 #endif
344 344
345 - dpy_update(s->ds, 0, 0, s->width, s->height); 345 + dpy_update(s->vga.ds, 0, 0, s->width, s->height);
346 } 346 }
347 347
348 #ifdef DIRECT_VRAM 348 #ifdef DIRECT_VRAM
@@ -383,7 +383,7 @@ static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, @@ -383,7 +383,7 @@ static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
383 # ifdef DIRECT_VRAM 383 # ifdef DIRECT_VRAM
384 uint8_t *vram = ds_get_data(s->ds); 384 uint8_t *vram = ds_get_data(s->ds);
385 # else 385 # else
386 - uint8_t *vram = s->vram_ptr; 386 + uint8_t *vram = s->vga.vram_ptr;
387 # endif 387 # endif
388 int bypl = s->bypp * s->width; 388 int bypl = s->bypp * s->width;
389 int width = s->bypp * w; 389 int width = s->bypp * w;
@@ -420,7 +420,7 @@ static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, @@ -420,7 +420,7 @@ static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
420 # ifdef DIRECT_VRAM 420 # ifdef DIRECT_VRAM
421 uint8_t *vram = ds_get_data(s->ds); 421 uint8_t *vram = ds_get_data(s->ds);
422 # else 422 # else
423 - uint8_t *vram = s->vram_ptr; 423 + uint8_t *vram = s->vga.vram_ptr;
424 # endif 424 # endif
425 int bypp = s->bypp; 425 int bypp = s->bypp;
426 int bypl = bypp * s->width; 426 int bypl = bypp * s->width;
@@ -485,8 +485,8 @@ static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, @@ -485,8 +485,8 @@ static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
485 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --) 485 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
486 c->mask[i] = ~c->mask[i]; 486 c->mask[i] = ~c->mask[i];
487 487
488 - if (s->ds->cursor_define)  
489 - s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y, 488 + if (s->vga.ds->cursor_define)
  489 + s->vga.ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
490 (uint8_t *) c->image, (uint8_t *) c->mask); 490 (uint8_t *) c->image, (uint8_t *) c->mask);
491 } 491 }
492 #endif 492 #endif
@@ -689,7 +689,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) @@ -689,7 +689,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
689 return 0x0; 689 return 0x0;
690 690
691 case SVGA_REG_VRAM_SIZE: 691 case SVGA_REG_VRAM_SIZE:
692 - return s->vram_size - SVGA_FIFO_SIZE; 692 + return s->vga.vram_size - SVGA_FIFO_SIZE;
693 693
694 case SVGA_REG_FB_SIZE: 694 case SVGA_REG_FB_SIZE:
695 return s->fb_size; 695 return s->fb_size;
@@ -703,14 +703,14 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) @@ -703,14 +703,14 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
703 caps |= SVGA_CAP_RECT_FILL; 703 caps |= SVGA_CAP_RECT_FILL;
704 #endif 704 #endif
705 #ifdef HW_MOUSE_ACCEL 705 #ifdef HW_MOUSE_ACCEL
706 - if (s->ds->mouse_set) 706 + if (s->vga.ds->mouse_set)
707 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | 707 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
708 SVGA_CAP_CURSOR_BYPASS; 708 SVGA_CAP_CURSOR_BYPASS;
709 #endif 709 #endif
710 return caps; 710 return caps;
711 711
712 case SVGA_REG_MEM_START: 712 case SVGA_REG_MEM_START:
713 - return s->vram_base + s->vram_size - SVGA_FIFO_SIZE; 713 + return s->vram_base + s->vga.vram_size - SVGA_FIFO_SIZE;
714 714
715 case SVGA_REG_MEM_SIZE: 715 case SVGA_REG_MEM_SIZE:
716 return SVGA_FIFO_SIZE; 716 return SVGA_FIFO_SIZE;
@@ -775,7 +775,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) @@ -775,7 +775,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
775 s->height = -1; 775 s->height = -1;
776 s->invalidated = 1; 776 s->invalidated = 1;
777 #ifdef EMBED_STDVGA 777 #ifdef EMBED_STDVGA
778 - s->invalidate(opaque); 778 + s->vga.invalidate(&s->vga);
779 #endif 779 #endif
780 if (s->enable) 780 if (s->enable)
781 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; 781 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
@@ -801,7 +801,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) @@ -801,7 +801,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
801 801
802 case SVGA_REG_CONFIG_DONE: 802 case SVGA_REG_CONFIG_DONE:
803 if (value) { 803 if (value) {
804 - s->fifo = (uint32_t *) &s->vram_ptr[s->vram_size - SVGA_FIFO_SIZE]; 804 + s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
805 /* Check range and alignment. */ 805 /* Check range and alignment. */
806 if ((CMD(min) | CMD(max) | 806 if ((CMD(min) | CMD(max) |
807 CMD(next_cmd) | CMD(stop)) & 3) 807 CMD(next_cmd) | CMD(stop)) & 3)
@@ -847,8 +847,8 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) @@ -847,8 +847,8 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
847 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); 847 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
848 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); 848 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
849 #ifdef HW_MOUSE_ACCEL 849 #ifdef HW_MOUSE_ACCEL
850 - if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)  
851 - s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); 850 + if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
  851 + s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
852 #endif 852 #endif
853 break; 853 break;
854 854
@@ -885,7 +885,7 @@ static inline void vmsvga_size(struct vmsvga_state_s *s) @@ -885,7 +885,7 @@ static inline void vmsvga_size(struct vmsvga_state_s *s)
885 if (s->new_width != s->width || s->new_height != s->height) { 885 if (s->new_width != s->width || s->new_height != s->height) {
886 s->width = s->new_width; 886 s->width = s->new_width;
887 s->height = s->new_height; 887 s->height = s->new_height;
888 - qemu_console_resize(s->ds, s->width, s->height); 888 + qemu_console_resize(s->vga.ds, s->width, s->height);
889 s->invalidated = 1; 889 s->invalidated = 1;
890 } 890 }
891 } 891 }
@@ -895,7 +895,7 @@ static void vmsvga_update_display(void *opaque) @@ -895,7 +895,7 @@ static void vmsvga_update_display(void *opaque)
895 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; 895 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
896 if (!s->enable) { 896 if (!s->enable) {
897 #ifdef EMBED_STDVGA 897 #ifdef EMBED_STDVGA
898 - s->update(opaque); 898 + s->vga.update(&s->vga);
899 #endif 899 #endif
900 return; 900 return;
901 } 901 }
@@ -963,7 +963,7 @@ static void vmsvga_invalidate_display(void *opaque) @@ -963,7 +963,7 @@ static void vmsvga_invalidate_display(void *opaque)
963 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; 963 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
964 if (!s->enable) { 964 if (!s->enable) {
965 #ifdef EMBED_STDVGA 965 #ifdef EMBED_STDVGA
966 - s->invalidate(opaque); 966 + s->vga.invalidate(&s->vga);
967 #endif 967 #endif
968 return; 968 return;
969 } 969 }
@@ -978,14 +978,14 @@ static void vmsvga_screen_dump(void *opaque, const char *filename) @@ -978,14 +978,14 @@ static void vmsvga_screen_dump(void *opaque, const char *filename)
978 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; 978 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
979 if (!s->enable) { 979 if (!s->enable) {
980 #ifdef EMBED_STDVGA 980 #ifdef EMBED_STDVGA
981 - s->screen_dump(opaque, filename); 981 + s->vga.screen_dump(&s->vga, filename);
982 #endif 982 #endif
983 return; 983 return;
984 } 984 }
985 985
986 if (s->depth == 32) { 986 if (s->depth == 32) {
987 DisplaySurface *ds = qemu_create_displaysurface_from(s->width, 987 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
988 - s->height, 32, ds_get_linesize(s->ds), s->vram_ptr); 988 + s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
989 ppm_save(filename, ds); 989 ppm_save(filename, ds);
990 qemu_free(ds); 990 qemu_free(ds);
991 } 991 }
@@ -995,8 +995,8 @@ static void vmsvga_text_update(void *opaque, console_ch_t *chardata) @@ -995,8 +995,8 @@ static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
995 { 995 {
996 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; 996 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
997 997
998 - if (s->text_update)  
999 - s->text_update(opaque, chardata); 998 + if (s->vga.text_update)
  999 + s->vga.text_update(&s->vga, chardata);
1000 } 1000 }
1001 1001
1002 #ifdef DIRECT_VRAM 1002 #ifdef DIRECT_VRAM
@@ -1116,7 +1116,7 @@ static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f) @@ -1116,7 +1116,7 @@ static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1116 1116
1117 s->invalidated = 1; 1117 s->invalidated = 1;
1118 if (s->config) 1118 if (s->config)
1119 - s->fifo = (uint32_t *) &s->vram_ptr[s->vram_size - SVGA_FIFO_SIZE]; 1119 + s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
1120 1120
1121 return 0; 1121 return 0;
1122 } 1122 }
@@ -1137,15 +1137,15 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size) @@ -1137,15 +1137,15 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
1137 s->vram_ptr = qemu_get_ram_ptr(s->vram_offset); 1137 s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
1138 #endif 1138 #endif
1139 1139
1140 - s->ds = graphic_console_init(vmsvga_update_display,  
1141 - vmsvga_invalidate_display,  
1142 - vmsvga_screen_dump,  
1143 - vmsvga_text_update, s); 1140 + s->vga.ds = graphic_console_init(vmsvga_update_display,
  1141 + vmsvga_invalidate_display,
  1142 + vmsvga_screen_dump,
  1143 + vmsvga_text_update, &s->vga);
1144 1144
1145 #ifdef CONFIG_BOCHS_VBE 1145 #ifdef CONFIG_BOCHS_VBE
1146 /* XXX: use optimized standard vga accesses */ 1146 /* XXX: use optimized standard vga accesses */
1147 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS, 1147 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1148 - vga_ram_size, s->vram_offset); 1148 + vga_ram_size, s->vga.vram_offset);
1149 #endif 1149 #endif
1150 } 1150 }
1151 1151
@@ -1204,9 +1204,9 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, @@ -1204,9 +1204,9 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1204 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read, 1204 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1205 vmsvga_vram_write, s); 1205 vmsvga_vram_write, s);
1206 #else 1206 #else
1207 - iomemtype = s->vram_offset | IO_MEM_RAM; 1207 + iomemtype = s->vga.vram_offset | IO_MEM_RAM;
1208 #endif 1208 #endif
1209 - cpu_register_physical_memory(s->vram_base, s->vram_size, 1209 + cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
1210 iomemtype); 1210 iomemtype);
1211 } 1211 }
1212 1212