Commit 4da0033e6ead7921dada84a3321e35f287db6887

Authored by aurel32
1 parent d2c7c9b8

target-ppc: fix srw on 64-bit targets

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5595 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 5 additions and 3 deletions
target-ppc/translate.c
@@ -2012,7 +2012,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) @@ -2012,7 +2012,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
2012 /* srw & srw. */ 2012 /* srw & srw. */
2013 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) 2013 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
2014 { 2014 {
2015 - TCGv temp; 2015 + TCGv temp, temp2;
2016 int l1, l2; 2016 int l1, l2;
2017 l1 = gen_new_label(); 2017 l1 = gen_new_label();
2018 l2 = gen_new_label(); 2018 l2 = gen_new_label();
@@ -2024,8 +2024,10 @@ GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER) @@ -2024,8 +2024,10 @@ GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
2024 tcg_gen_br(l2); 2024 tcg_gen_br(l2);
2025 gen_set_label(l1); 2025 gen_set_label(l1);
2026 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f); 2026 tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
2027 - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);  
2028 - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2027 + temp2 = tcg_temp_new(TCG_TYPE_TL);
  2028 + tcg_gen_ext32u_tl(temp2, cpu_gpr[rS(ctx->opcode)]);
  2029 + tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], temp2, temp);
  2030 + tcg_temp_free(temp2);
2029 gen_set_label(l2); 2031 gen_set_label(l2);
2030 tcg_temp_free(temp); 2032 tcg_temp_free(temp);
2031 if (unlikely(Rc(ctx->opcode) != 0)) 2033 if (unlikely(Rc(ctx->opcode) != 0))