Commit 4d7a0880ca35ea95d30583d137b1558d4dd166bc

Authored by blueswir1
1 parent 22548760

Fix compiler warnings in common files

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4405 c046a42c-6fe2-441c-8c8c-71466251a162
cpu-all.h
@@ -452,7 +452,7 @@ static inline uint64_t ldq_be_p(void *ptr) @@ -452,7 +452,7 @@ static inline uint64_t ldq_be_p(void *ptr)
452 { 452 {
453 uint32_t a,b; 453 uint32_t a,b;
454 a = ldl_be_p(ptr); 454 a = ldl_be_p(ptr);
455 - b = ldl_be_p(ptr+4); 455 + b = ldl_be_p((uint8_t *)ptr + 4);
456 return (((uint64_t)a<<32)|b); 456 return (((uint64_t)a<<32)|b);
457 } 457 }
458 458
@@ -489,7 +489,7 @@ static inline void stl_be_p(void *ptr, int v) @@ -489,7 +489,7 @@ static inline void stl_be_p(void *ptr, int v)
489 static inline void stq_be_p(void *ptr, uint64_t v) 489 static inline void stq_be_p(void *ptr, uint64_t v)
490 { 490 {
491 stl_be_p(ptr, v >> 32); 491 stl_be_p(ptr, v >> 32);
492 - stl_be_p(ptr + 4, v); 492 + stl_be_p((uint8_t *)ptr + 4, v);
493 } 493 }
494 494
495 /* float access */ 495 /* float access */
@@ -518,7 +518,7 @@ static inline float64 ldfq_be_p(void *ptr) @@ -518,7 +518,7 @@ static inline float64 ldfq_be_p(void *ptr)
518 { 518 {
519 CPU_DoubleU u; 519 CPU_DoubleU u;
520 u.l.upper = ldl_be_p(ptr); 520 u.l.upper = ldl_be_p(ptr);
521 - u.l.lower = ldl_be_p(ptr + 4); 521 + u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
522 return u.d; 522 return u.d;
523 } 523 }
524 524
@@ -527,7 +527,7 @@ static inline void stfq_be_p(void *ptr, float64 v) @@ -527,7 +527,7 @@ static inline void stfq_be_p(void *ptr, float64 v)
527 CPU_DoubleU u; 527 CPU_DoubleU u;
528 u.d = v; 528 u.d = v;
529 stl_be_p(ptr, u.l.upper); 529 stl_be_p(ptr, u.l.upper);
530 - stl_be_p(ptr + 4, u.l.lower); 530 + stl_be_p((uint8_t *)ptr + 4, u.l.lower);
531 } 531 }
532 532
533 #else 533 #else
cpu-exec.c
@@ -640,7 +640,7 @@ int cpu_exec(CPUState *env1) @@ -640,7 +640,7 @@ int cpu_exec(CPUState *env1)
640 jump. */ 640 jump. */
641 { 641 {
642 if (next_tb != 0 && 642 if (next_tb != 0 &&
643 -#if USE_KQEMU 643 +#ifdef USE_KQEMU
644 (env->kqemu_enabled != 2) && 644 (env->kqemu_enabled != 2) &&
645 #endif 645 #endif
646 tb->page_addr[1] == -1) { 646 tb->page_addr[1] == -1) {
dis-asm.h
@@ -396,7 +396,6 @@ extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*)); @@ -396,7 +396,6 @@ extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*));
396 extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); 396 extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*));
397 extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); 397 extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*));
398 extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*)); 398 extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*));
399 -extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));  
400 extern int print_insn_s390 PARAMS ((bfd_vma, disassemble_info*)); 399 extern int print_insn_s390 PARAMS ((bfd_vma, disassemble_info*));
401 extern int print_insn_crisv32 PARAMS ((bfd_vma, disassemble_info*)); 400 extern int print_insn_crisv32 PARAMS ((bfd_vma, disassemble_info*));
402 401
exec-all.h
@@ -93,13 +93,13 @@ void tlb_flush(CPUState *env, int flush_global); @@ -93,13 +93,13 @@ void tlb_flush(CPUState *env, int flush_global);
93 int tlb_set_page_exec(CPUState *env, target_ulong vaddr, 93 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
94 target_phys_addr_t paddr, int prot, 94 target_phys_addr_t paddr, int prot,
95 int mmu_idx, int is_softmmu); 95 int mmu_idx, int is_softmmu);
96 -static inline int tlb_set_page(CPUState *env, target_ulong vaddr, 96 +static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
97 target_phys_addr_t paddr, int prot, 97 target_phys_addr_t paddr, int prot,
98 int mmu_idx, int is_softmmu) 98 int mmu_idx, int is_softmmu)
99 { 99 {
100 if (prot & PAGE_READ) 100 if (prot & PAGE_READ)
101 prot |= PAGE_EXEC; 101 prot |= PAGE_EXEC;
102 - return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); 102 + return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
103 } 103 }
104 104
105 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 105 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
@@ -550,7 +550,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, @@ -550,7 +550,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
550 #endif 550 #endif
551 551
552 #if defined(CONFIG_USER_ONLY) 552 #if defined(CONFIG_USER_ONLY)
553 -static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) 553 +static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
554 { 554 {
555 return addr; 555 return addr;
556 } 556 }
@@ -558,25 +558,25 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) @@ -558,25 +558,25 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
558 /* NOTE: this function can trigger an exception */ 558 /* NOTE: this function can trigger an exception */
559 /* NOTE2: the returned address is not exactly the physical address: it 559 /* NOTE2: the returned address is not exactly the physical address: it
560 is the offset relative to phys_ram_base */ 560 is the offset relative to phys_ram_base */
561 -static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) 561 +static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
562 { 562 {
563 - int mmu_idx, index, pd; 563 + int mmu_idx, page_index, pd;
564 564
565 - index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);  
566 - mmu_idx = cpu_mmu_index(env);  
567 - if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code != 565 + page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
  566 + mmu_idx = cpu_mmu_index(env1);
  567 + if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
568 (addr & TARGET_PAGE_MASK), 0)) { 568 (addr & TARGET_PAGE_MASK), 0)) {
569 ldub_code(addr); 569 ldub_code(addr);
570 } 570 }
571 - pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; 571 + pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
572 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { 572 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
573 #if defined(TARGET_SPARC) || defined(TARGET_MIPS) 573 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
574 do_unassigned_access(addr, 0, 1, 0); 574 do_unassigned_access(addr, 0, 1, 0);
575 #else 575 #else
576 - cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); 576 + cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
577 #endif 577 #endif
578 } 578 }
579 - return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base; 579 + return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
580 } 580 }
581 #endif 581 #endif
582 582
softmmu_header.h
@@ -222,20 +222,20 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE @@ -222,20 +222,20 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE
222 222
223 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) 223 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
224 { 224 {
225 - int index; 225 + int page_index;
226 RES_TYPE res; 226 RES_TYPE res;
227 target_ulong addr; 227 target_ulong addr;
228 unsigned long physaddr; 228 unsigned long physaddr;
229 int mmu_idx; 229 int mmu_idx;
230 230
231 addr = ptr; 231 addr = ptr;
232 - index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); 232 + page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
233 mmu_idx = CPU_MMU_INDEX; 233 mmu_idx = CPU_MMU_INDEX;
234 - if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ != 234 + if (__builtin_expect(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
235 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { 235 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
236 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx); 236 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
237 } else { 237 } else {
238 - physaddr = addr + env->tlb_table[mmu_idx][index].addend; 238 + physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
239 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr); 239 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
240 } 240 }
241 return res; 241 return res;
@@ -244,19 +244,19 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) @@ -244,19 +244,19 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
244 #if DATA_SIZE <= 2 244 #if DATA_SIZE <= 2
245 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) 245 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
246 { 246 {
247 - int res, index; 247 + int res, page_index;
248 target_ulong addr; 248 target_ulong addr;
249 unsigned long physaddr; 249 unsigned long physaddr;
250 int mmu_idx; 250 int mmu_idx;
251 251
252 addr = ptr; 252 addr = ptr;
253 - index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); 253 + page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
254 mmu_idx = CPU_MMU_INDEX; 254 mmu_idx = CPU_MMU_INDEX;
255 - if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ != 255 + if (__builtin_expect(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
256 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { 256 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
257 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx); 257 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
258 } else { 258 } else {
259 - physaddr = addr + env->tlb_table[mmu_idx][index].addend; 259 + physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
260 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr); 260 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
261 } 261 }
262 return res; 262 return res;
@@ -269,19 +269,19 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) @@ -269,19 +269,19 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
269 269
270 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v) 270 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
271 { 271 {
272 - int index; 272 + int page_index;
273 target_ulong addr; 273 target_ulong addr;
274 unsigned long physaddr; 274 unsigned long physaddr;
275 int mmu_idx; 275 int mmu_idx;
276 276
277 addr = ptr; 277 addr = ptr;
278 - index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); 278 + page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
279 mmu_idx = CPU_MMU_INDEX; 279 mmu_idx = CPU_MMU_INDEX;
280 - if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_write != 280 + if (__builtin_expect(env->tlb_table[mmu_idx][page_index].addr_write !=
281 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) { 281 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
282 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx); 282 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
283 } else { 283 } else {
284 - physaddr = addr + env->tlb_table[mmu_idx][index].addend; 284 + physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
285 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v); 285 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
286 } 286 }
287 } 287 }
sysemu.h
@@ -130,8 +130,8 @@ typedef struct DriveInfo { @@ -130,8 +130,8 @@ typedef struct DriveInfo {
130 #define MAX_SCSI_DEVS 7 130 #define MAX_SCSI_DEVS 7
131 #define MAX_DRIVES 32 131 #define MAX_DRIVES 32
132 132
133 -int nb_drives;  
134 -DriveInfo drives_table[MAX_DRIVES+1]; 133 +extern int nb_drives;
  134 +extern DriveInfo drives_table[MAX_DRIVES+1];
135 135
136 extern int drive_get_index(BlockInterfaceType type, int bus, int unit); 136 extern int drive_get_index(BlockInterfaceType type, int bus, int unit);
137 extern int drive_get_max_bus(BlockInterfaceType type); 137 extern int drive_get_max_bus(BlockInterfaceType type);