Fix 64-bit host printf format mismatches.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3564 c046a42c-6fe2-441c-8c8c-71466251a162

Fix 64-bit host printf format mismatches.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3564 c046a42c-6fe2-441c-8c8c-71466251a162
pbrook
1 parent 2a324a26
Showing 8 changed files with 20 additions and 18 deletions
hw/integratorcp.c
hw/pl011.c
hw/pl050.c
hw/pl080.c
hw/pl110.c
hw/pl181.c
hw/pl190.c
hw/smc91c111.c
@@ -99,7 +99,7 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
         return 0;
     default:
         cpu_abort (cpu_single_env,
-            "integratorcm_read: Unimplemented offset 0x%x\n", offset);
+            "integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
         return 0;
     }
 }
@@ -207,7 +207,7 @@ static void integratorcm_write(void *opaque, target_phys_addr_t offset,
         break;
     default:
         cpu_abort (cpu_single_env,
-            "integratorcm_write: Unimplemented offset 0x%x\n", offset);
+            "integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
         break;
     }
 }
@@ -414,7 +414,8 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
     case 3: /* CP_DECODE */
         return 0x11;
     default:
-        cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
+                   (int)offset);
         return 0;
     }
 }
@@ -431,7 +432,8 @@ static void icp_control_write(void *opaque, target_phys_addr_t offset,
         /* Nothing interesting implemented yet.  */
         break;
     default:
-        cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
+                   (int)offset);
     }
 }
 static CPUReadMemoryFunc *icp_control_readfn[] = {
@@ -99,7 +99,7 @@ static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
     case 18: /* UARTDMACR */
         return s->dmacr;
     default:
-        cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -172,7 +172,7 @@ static void pl011_write(void *opaque, target_phys_addr_t offset,
             cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
         break;
     default:
-        cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
     }
 }
@@ -79,7 +79,7 @@ static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
     case 4: /* KMIIR */
         return s->pending | 2;
     default:
-        cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -108,7 +108,7 @@ static void pl050_write(void *opaque, target_phys_addr_t offset,
         s->clk = value;
         return;
     default:
-        cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", (int)offset);
     }
 }
 static CPUReadMemoryFunc *pl050_readfn[] = {
@@ -243,7 +243,7 @@ static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
         return s->sync;
     default:
     bad_offset:
-        cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", offset);
+        cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -305,7 +305,7 @@ static void pl080_write(void *opaque, target_phys_addr_t offset,
         break;
     default:
     bad_offset:
-        cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", offset);
+        cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", (int)offset);
     }
     pl080_update(s);
 }
@@ -326,7 +326,7 @@ static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
     case 12: /* LCDLPCURR */
         return s->lpbase;
     default:
-        cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -393,7 +393,7 @@ static void pl110_write(void *opaque, target_phys_addr_t offset,
         pl110_update(s);
         break;
     default:
-        cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
     }
 }
@@ -333,7 +333,7 @@ static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
             return value;
         }
     default:
-        cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -405,7 +405,7 @@ static void pl181_write(void *opaque, target_phys_addr_t offset,
         }
         break;
     default:
-        cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", (int)offset);
     }
     pl181_update(s);
 }
@@ -139,7 +139,7 @@ static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
     case 13: /* DEFVECTADDR */
         return s->vect_addr[16];
     default:
-        cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", offset);
+        cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -197,7 +197,7 @@ static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
             cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
         break;
     default:
-        cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", offset);
+        cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset);
         return;
     }
     pl190_update(s);
@@ -413,7 +413,7 @@ static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
         break;
     }
     cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
-               s->bank, offset);
+               s->bank, (int)offset);
 }
 static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
@@ -555,7 +555,7 @@ static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
         break;
     }
     cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
-               s->bank, offset);
+               s->bank, (int)offset);
     return 0;
 }