Commit 4b8b8b76d460804c7318a85cfe5352876f2430f7
1 parent
a23a663b
Document the shift values
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4243 c046a42c-6fe2-441c-8c8c-71466251a162
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18 additions
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12 deletions
target-sparc/cpu.h
| @@ -71,10 +71,14 @@ | @@ -71,10 +71,14 @@ | ||
| 71 | #define TT_TRAP 0x100 | 71 | #define TT_TRAP 0x100 |
| 72 | #endif | 72 | #endif |
| 73 | 73 | ||
| 74 | -#define PSR_NEG (1<<23) | ||
| 75 | -#define PSR_ZERO (1<<22) | ||
| 76 | -#define PSR_OVF (1<<21) | ||
| 77 | -#define PSR_CARRY (1<<20) | 74 | +#define PSR_NEG_SHIFT 23 |
| 75 | +#define PSR_NEG (1 << PSR_NEG_SHIFT) | ||
| 76 | +#define PSR_ZERO_SHIFT 22 | ||
| 77 | +#define PSR_ZERO (1 << PSR_ZERO_SHIFT) | ||
| 78 | +#define PSR_OVF_SHIFT 21 | ||
| 79 | +#define PSR_OVF (1 << PSR_OVF_SHIFT) | ||
| 80 | +#define PSR_CARRY_SHIFT 20 | ||
| 81 | +#define PSR_CARRY (1 << PSR_CARRY_SHIFT) | ||
| 78 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) | 82 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
| 79 | #define PSR_EF (1<<12) | 83 | #define PSR_EF (1<<12) |
| 80 | #define PSR_PIL 0xf00 | 84 | #define PSR_PIL 0xf00 |
| @@ -141,8 +145,10 @@ | @@ -141,8 +145,10 @@ | ||
| 141 | #define FSR_FTT_SEQ_ERROR (4 << 14) | 145 | #define FSR_FTT_SEQ_ERROR (4 << 14) |
| 142 | #define FSR_FTT_INVAL_FPR (6 << 14) | 146 | #define FSR_FTT_INVAL_FPR (6 << 14) |
| 143 | 147 | ||
| 144 | -#define FSR_FCC1 (1<<11) | ||
| 145 | -#define FSR_FCC0 (1<<10) | 148 | +#define FSR_FCC1_SHIFT 11 |
| 149 | +#define FSR_FCC1 (1 << FSR_FCC1_SHIFT) | ||
| 150 | +#define FSR_FCC0_SHIFT 10 | ||
| 151 | +#define FSR_FCC0 (1 << FSR_FCC0_SHIFT) | ||
| 146 | 152 | ||
| 147 | /* MMU */ | 153 | /* MMU */ |
| 148 | #define MMU_E (1<<0) | 154 | #define MMU_E (1<<0) |
target-sparc/translate.c
| @@ -266,28 +266,28 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, | @@ -266,28 +266,28 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, | ||
| 266 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) | 266 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) |
| 267 | { | 267 | { |
| 268 | tcg_gen_extu_i32_tl(reg, src); | 268 | tcg_gen_extu_i32_tl(reg, src); |
| 269 | - tcg_gen_shri_tl(reg, reg, 23); | 269 | + tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
| 270 | tcg_gen_andi_tl(reg, reg, 0x1); | 270 | tcg_gen_andi_tl(reg, reg, 0x1); |
| 271 | } | 271 | } |
| 272 | 272 | ||
| 273 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) | 273 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) |
| 274 | { | 274 | { |
| 275 | tcg_gen_extu_i32_tl(reg, src); | 275 | tcg_gen_extu_i32_tl(reg, src); |
| 276 | - tcg_gen_shri_tl(reg, reg, 22); | 276 | + tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
| 277 | tcg_gen_andi_tl(reg, reg, 0x1); | 277 | tcg_gen_andi_tl(reg, reg, 0x1); |
| 278 | } | 278 | } |
| 279 | 279 | ||
| 280 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) | 280 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) |
| 281 | { | 281 | { |
| 282 | tcg_gen_extu_i32_tl(reg, src); | 282 | tcg_gen_extu_i32_tl(reg, src); |
| 283 | - tcg_gen_shri_tl(reg, reg, 21); | 283 | + tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
| 284 | tcg_gen_andi_tl(reg, reg, 0x1); | 284 | tcg_gen_andi_tl(reg, reg, 0x1); |
| 285 | } | 285 | } |
| 286 | 286 | ||
| 287 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) | 287 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) |
| 288 | { | 288 | { |
| 289 | tcg_gen_extu_i32_tl(reg, src); | 289 | tcg_gen_extu_i32_tl(reg, src); |
| 290 | - tcg_gen_shri_tl(reg, reg, 20); | 290 | + tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
| 291 | tcg_gen_andi_tl(reg, reg, 0x1); | 291 | tcg_gen_andi_tl(reg, reg, 0x1); |
| 292 | } | 292 | } |
| 293 | 293 | ||
| @@ -965,7 +965,7 @@ static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, | @@ -965,7 +965,7 @@ static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, | ||
| 965 | unsigned int fcc_offset) | 965 | unsigned int fcc_offset) |
| 966 | { | 966 | { |
| 967 | tcg_gen_extu_i32_tl(reg, src); | 967 | tcg_gen_extu_i32_tl(reg, src); |
| 968 | - tcg_gen_shri_tl(reg, reg, 10 + fcc_offset); | 968 | + tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); |
| 969 | tcg_gen_andi_tl(reg, reg, 0x1); | 969 | tcg_gen_andi_tl(reg, reg, 0x1); |
| 970 | } | 970 | } |
| 971 | 971 | ||
| @@ -973,7 +973,7 @@ static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, | @@ -973,7 +973,7 @@ static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, | ||
| 973 | unsigned int fcc_offset) | 973 | unsigned int fcc_offset) |
| 974 | { | 974 | { |
| 975 | tcg_gen_extu_i32_tl(reg, src); | 975 | tcg_gen_extu_i32_tl(reg, src); |
| 976 | - tcg_gen_shri_tl(reg, reg, 11 + fcc_offset); | 976 | + tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); |
| 977 | tcg_gen_andi_tl(reg, reg, 0x1); | 977 | tcg_gen_andi_tl(reg, reg, 0x1); |
| 978 | } | 978 | } |
| 979 | 979 |