gwj / at91sam9263 · Commits

Commit 4b2eb8d2759aa575062c587cded89ae347ce1317

Authored by ths
1 parent f01be154

Use TCG registers for most CPU register accesses. 

Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5253 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 52 additions and 17 deletions
target-mips/translate.c
  View file @4b2eb8d
... ... @@ -423,7 +423,9 @@ enum {
423 423 };
424 424  
425 425 /* global register indices */
426   -static TCGv cpu_env, bcond, btarget;
  426 +static TCGv cpu_env, cpu_gpr[32], cpu_PC;
  427 +static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
  428 +static TCGv cpu_dspctrl, bcond, btarget;
427 429 static TCGv fpu_fpr32[32], fpu_fpr32h[32], fpu_fpr64[32], fpu_fcr0, fpu_fcr31;
428 430  
429 431 #include "gen-icount.h"
... ... @@ -542,6 +544,15 @@ static const char *regnames[] =
542 544 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
543 545 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
544 546  
  547 +static const char *regnames_HI[] =
  548 + { "HI0", "HI1", "HI2", "HI3", };
  549 +
  550 +static const char *regnames_LO[] =
  551 + { "LO0", "LO1", "LO2", "LO3", };
  552 +
  553 +static const char *regnames_ACX[] =
  554 + { "ACX0", "ACX1", "ACX2", "ACX3", };
  555 +
545 556 static const char *fregnames[] =
546 557 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
547 558 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
... ... @@ -584,40 +595,44 @@ static inline void gen_load_gpr (TCGv t, int reg)
584 595 if (reg == 0)
585 596 tcg_gen_movi_tl(t, 0);
586 597 else
587   - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, active_tc.gpr) +
588   - sizeof(target_ulong) * reg);
  598 + tcg_gen_mov_tl(t, cpu_gpr[reg]);
589 599 }
590 600  
591 601 static inline void gen_store_gpr (TCGv t, int reg)
592 602 {
593 603 if (reg != 0)
594   - tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, active_tc.gpr) +
595   - sizeof(target_ulong) * reg);
  604 + tcg_gen_mov_tl(cpu_gpr[reg], t);
596 605 }
597 606  
598 607 /* Moves to/from HI and LO registers. */
  608 +static inline void gen_load_HI (TCGv t, int reg)
  609 +{
  610 + tcg_gen_mov_tl(t, cpu_HI[reg]);
  611 +}
  612 +
  613 +static inline void gen_store_HI (TCGv t, int reg)
  614 +{
  615 + tcg_gen_mov_tl(cpu_HI[reg], t);
  616 +}
  617 +
599 618 static inline void gen_load_LO (TCGv t, int reg)
600 619 {
601   - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, active_tc.LO) +
602   - sizeof(target_ulong) * reg);
  620 + tcg_gen_mov_tl(t, cpu_LO[reg]);
603 621 }
604 622  
605 623 static inline void gen_store_LO (TCGv t, int reg)
606 624 {
607   - tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, active_tc.LO) +
608   - sizeof(target_ulong) * reg);
  625 + tcg_gen_mov_tl(cpu_LO[reg], t);
609 626 }
610 627  
611   -static inline void gen_load_HI (TCGv t, int reg)
  628 +static inline void gen_load_ACX (TCGv t, int reg)
612 629 {
613   - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, active_tc.HI) +
614   - sizeof(target_ulong) * reg);
  630 + tcg_gen_mov_tl(t, cpu_ACX[reg]);
615 631 }
616 632  
617   -static inline void gen_store_HI (TCGv t, int reg)
  633 +static inline void gen_store_ACX (TCGv t, int reg)
618 634 {
619   - tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, active_tc.HI) +
620   - sizeof(target_ulong) * reg);
  635 + tcg_gen_mov_tl(cpu_ACX[reg], t);
621 636 }
622 637  
623 638 /* Moves to/from shadow registers. */
... ... @@ -821,7 +836,7 @@ static inline void gen_save_pc(target_ulong pc)
821 836 TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
822 837  
823 838 tcg_gen_movi_tl(r_tmp, pc);
824   - tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, active_tc.PC));
  839 + tcg_gen_mov_tl(cpu_PC, r_tmp);
825 840 tcg_temp_free(r_tmp);
826 841 }
827 842  
... ... @@ -8441,7 +8456,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
8441 8456 case MIPS_HFLAG_BR:
8442 8457 /* unconditional branch to register */
8443 8458 MIPS_DEBUG("branch to register");
8444   - tcg_gen_st_tl(btarget, cpu_env, offsetof(CPUState, active_tc.PC));
  8459 + tcg_gen_mov_tl(cpu_PC, btarget);
8445 8460 tcg_gen_exit_tb(0);
8446 8461 break;
8447 8462 default:
... ... @@ -8714,6 +8729,26 @@ static void mips_tcg_init(void)
8714 8729 return;
8715 8730  
8716 8731 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
  8732 + for (i = 0; i < 32; i++)
  8733 + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  8734 + offsetof(CPUState, active_tc.gpr[i]),
  8735 + regnames[i]);
  8736 + cpu_PC = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  8737 + offsetof(CPUState, active_tc.PC), "PC");
  8738 + for (i = 0; i < MIPS_DSP_ACC; i++) {
  8739 + cpu_HI[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  8740 + offsetof(CPUState, active_tc.HI[i]),
  8741 + regnames_HI[i]);
  8742 + cpu_LO[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  8743 + offsetof(CPUState, active_tc.LO[i]),
  8744 + regnames_LO[i]);
  8745 + cpu_ACX[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  8746 + offsetof(CPUState, active_tc.ACX[i]),
  8747 + regnames_ACX[i]);
  8748 + }
  8749 + cpu_dspctrl = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
  8750 + offsetof(CPUState, active_tc.DSPControl),
  8751 + "DSPControl");
8717 8752 bcond = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
8718 8753 offsetof(CPUState, bcond), "bcond");
8719 8754 btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
... ...