Commit 4a1e6beab60d9d105fcc56f3d568044390ef7e9e
1 parent
69b5cae1
ETRAX: Add a dummy tempsensor and correct the NAND flash model.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6202 c046a42c-6fe2-441c-8c8c-71466251a162
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98 additions
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6 deletions
hw/axis_dev88.c
@@ -84,12 +84,88 @@ static CPUWriteMemoryFunc *nand_write[] = { | @@ -84,12 +84,88 @@ static CPUWriteMemoryFunc *nand_write[] = { | ||
84 | &nand_writel, | 84 | &nand_writel, |
85 | }; | 85 | }; |
86 | 86 | ||
87 | -#define RW_PA_DOUT 0 | ||
88 | -#define R_PA_DIN 1 | ||
89 | -#define RW_PA_OE 2 | ||
90 | -struct gpio_state_t | 87 | + |
88 | +struct tempsensor_t | ||
89 | +{ | ||
90 | + unsigned int shiftreg; | ||
91 | + unsigned int count; | ||
92 | + enum { | ||
93 | + ST_OUT, ST_IN, ST_Z | ||
94 | + } state; | ||
95 | + | ||
96 | + uint16_t regs[3]; | ||
97 | +}; | ||
98 | + | ||
99 | +static void tempsensor_clkedge(struct tempsensor_t *s, | ||
100 | + unsigned int clk, unsigned int data_in) | ||
101 | +{ | ||
102 | + D(printf("%s clk=%d state=%d sr=%x\n", __func__, | ||
103 | + clk, s->state, s->shiftreg)); | ||
104 | + if (s->count == 0) { | ||
105 | + s->count = 16; | ||
106 | + s->state = ST_OUT; | ||
107 | + } | ||
108 | + switch (s->state) { | ||
109 | + case ST_OUT: | ||
110 | + /* Output reg is clocked at negedge. */ | ||
111 | + if (!clk) { | ||
112 | + s->count--; | ||
113 | + s->shiftreg <<= 1; | ||
114 | + if (s->count == 0) { | ||
115 | + s->shiftreg = 0; | ||
116 | + s->state = ST_IN; | ||
117 | + s->count = 16; | ||
118 | + } | ||
119 | + } | ||
120 | + break; | ||
121 | + case ST_Z: | ||
122 | + if (clk) { | ||
123 | + s->count--; | ||
124 | + if (s->count == 0) { | ||
125 | + s->shiftreg = 0; | ||
126 | + s->state = ST_OUT; | ||
127 | + s->count = 16; | ||
128 | + } | ||
129 | + } | ||
130 | + break; | ||
131 | + case ST_IN: | ||
132 | + /* Indata is sampled at posedge. */ | ||
133 | + if (clk) { | ||
134 | + s->count--; | ||
135 | + s->shiftreg <<= 1; | ||
136 | + s->shiftreg |= data_in & 1; | ||
137 | + if (s->count == 0) { | ||
138 | + D(printf("%s cfgreg=%x\n", __func__, s->shiftreg)); | ||
139 | + s->regs[0] = s->shiftreg; | ||
140 | + s->state = ST_OUT; | ||
141 | + s->count = 16; | ||
142 | + | ||
143 | + if ((s->regs[0] & 0xff) == 0) { | ||
144 | + /* 25 degrees celcius. */ | ||
145 | + s->shiftreg = 0x0b9f; | ||
146 | + } else if ((s->regs[0] & 0xff) == 0xff) { | ||
147 | + /* Sensor ID, 0x8100 LM70. */ | ||
148 | + s->shiftreg = 0x8100; | ||
149 | + } else | ||
150 | + printf("Invalid tempsens state %x\n", s->regs[0]); | ||
151 | + } | ||
152 | + } | ||
153 | + break; | ||
154 | + } | ||
155 | +} | ||
156 | + | ||
157 | + | ||
158 | +#define RW_PA_DOUT 0x00 | ||
159 | +#define R_PA_DIN 0x01 | ||
160 | +#define RW_PA_OE 0x02 | ||
161 | +#define RW_PD_DOUT 0x10 | ||
162 | +#define R_PD_DIN 0x11 | ||
163 | +#define RW_PD_OE 0x12 | ||
164 | + | ||
165 | +static struct gpio_state_t | ||
91 | { | 166 | { |
92 | struct nand_state_t *nand; | 167 | struct nand_state_t *nand; |
168 | + struct tempsensor_t tempsensor; | ||
93 | uint32_t regs[0x5c / 4]; | 169 | uint32_t regs[0x5c / 4]; |
94 | } gpio_state; | 170 | } gpio_state; |
95 | 171 | ||
@@ -107,6 +183,13 @@ static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) | @@ -107,6 +183,13 @@ static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) | ||
107 | /* Encode pins from the nand. */ | 183 | /* Encode pins from the nand. */ |
108 | r |= s->nand->rdy << 7; | 184 | r |= s->nand->rdy << 7; |
109 | break; | 185 | break; |
186 | + case R_PD_DIN: | ||
187 | + r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE]; | ||
188 | + | ||
189 | + /* Encode temp sensor pins. */ | ||
190 | + r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4; | ||
191 | + break; | ||
192 | + | ||
110 | default: | 193 | default: |
111 | r = s->regs[addr]; | 194 | r = s->regs[addr]; |
112 | break; | 195 | break; |
@@ -131,6 +214,15 @@ static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | @@ -131,6 +214,15 @@ static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | ||
131 | 214 | ||
132 | s->regs[addr] = value; | 215 | s->regs[addr] = value; |
133 | break; | 216 | break; |
217 | + | ||
218 | + case RW_PD_DOUT: | ||
219 | + /* Temp sensor clk. */ | ||
220 | + if ((s->regs[addr] ^ value) & 2) | ||
221 | + tempsensor_clkedge(&s->tempsensor, !!(value & 2), | ||
222 | + !!(value & 16)); | ||
223 | + s->regs[addr] = value; | ||
224 | + break; | ||
225 | + | ||
134 | default: | 226 | default: |
135 | s->regs[addr] = value; | 227 | s->regs[addr] = value; |
136 | break; | 228 | break; |
@@ -194,13 +286,13 @@ void axisdev88_init (ram_addr_t ram_size, int vga_ram_size, | @@ -194,13 +286,13 @@ void axisdev88_init (ram_addr_t ram_size, int vga_ram_size, | ||
194 | 286 | ||
195 | 287 | ||
196 | /* Attach a NAND flash to CS1. */ | 288 | /* Attach a NAND flash to CS1. */ |
197 | - nand_state.nand = nand_init(NAND_MFR_STMICRO, 0xf1); | 289 | + nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39); |
198 | nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state); | 290 | nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state); |
199 | cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); | 291 | cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); |
200 | 292 | ||
201 | gpio_state.nand = &nand_state; | 293 | gpio_state.nand = &nand_state; |
202 | gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state); | 294 | gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state); |
203 | - cpu_register_physical_memory(0x3001a000, 0x1c, gpio_regs); | 295 | + cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); |
204 | 296 | ||
205 | 297 | ||
206 | pic = etraxfs_pic_init(env, 0x3001c000); | 298 | pic = etraxfs_pic_init(env, 0x3001c000); |