Commit 49e6637386acb8824114ed10308ed7869472ec0f
1 parent
5b0f0bec
Sparc32: convert eccmemctl to qdev
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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2 changed files
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37 additions
and
17 deletions
hw/eccmemctl.c
| @@ -21,9 +21,9 @@ | @@ -21,9 +21,9 @@ | ||
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. | 22 | * THE SOFTWARE. |
| 23 | */ | 23 | */ |
| 24 | -#include "hw.h" | 24 | + |
| 25 | #include "sun4m.h" | 25 | #include "sun4m.h" |
| 26 | -#include "sysemu.h" | 26 | +#include "sysbus.h" |
| 27 | 27 | ||
| 28 | //#define DEBUG_ECC | 28 | //#define DEBUG_ECC |
| 29 | 29 | ||
| @@ -126,6 +126,7 @@ | @@ -126,6 +126,7 @@ | ||
| 126 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) | 126 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
| 127 | 127 | ||
| 128 | typedef struct ECCState { | 128 | typedef struct ECCState { |
| 129 | + SysBusDevice busdev; | ||
| 129 | qemu_irq irq; | 130 | qemu_irq irq; |
| 130 | uint32_t regs[ECC_NREGS]; | 131 | uint32_t regs[ECC_NREGS]; |
| 131 | uint8_t diag[ECC_DIAG_SIZE]; | 132 | uint8_t diag[ECC_DIAG_SIZE]; |
| @@ -314,27 +315,46 @@ static void ecc_reset(void *opaque) | @@ -314,27 +315,46 @@ static void ecc_reset(void *opaque) | ||
| 314 | s->regs[ECC_ECR1] = 0; | 315 | s->regs[ECC_ECR1] = 0; |
| 315 | } | 316 | } |
| 316 | 317 | ||
| 317 | -void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) | 318 | +static void ecc_init1(SysBusDevice *dev) |
| 318 | { | 319 | { |
| 319 | int ecc_io_memory; | 320 | int ecc_io_memory; |
| 320 | - ECCState *s; | ||
| 321 | - | ||
| 322 | - s = qemu_mallocz(sizeof(ECCState)); | ||
| 323 | - | ||
| 324 | - s->version = version; | ||
| 325 | - s->regs[0] = version; | ||
| 326 | - s->irq = irq; | 321 | + ECCState *s = FROM_SYSBUS(ECCState, dev); |
| 327 | 322 | ||
| 323 | + sysbus_init_irq(dev, &s->irq); | ||
| 324 | + s->version = qdev_get_prop_int(&dev->qdev, "version", -1); | ||
| 325 | + s->regs[0] = s->version; | ||
| 328 | ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s); | 326 | ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s); |
| 329 | - cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory); | ||
| 330 | - if (version == ECC_MCC) { // SS-600MP only | 327 | + sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory); |
| 328 | + | ||
| 329 | + if (s->version == ECC_MCC) { // SS-600MP only | ||
| 331 | ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read, | 330 | ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read, |
| 332 | ecc_diag_mem_write, s); | 331 | ecc_diag_mem_write, s); |
| 333 | - cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE, | ||
| 334 | - ecc_io_memory); | 332 | + sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory); |
| 335 | } | 333 | } |
| 336 | - register_savevm("ECC", base, 3, ecc_save, ecc_load, s); | 334 | + register_savevm("ECC", -1, 3, ecc_save, ecc_load, s); |
| 337 | qemu_register_reset(ecc_reset, s); | 335 | qemu_register_reset(ecc_reset, s); |
| 338 | ecc_reset(s); | 336 | ecc_reset(s); |
| 339 | - return s; | ||
| 340 | } | 337 | } |
| 338 | + | ||
| 339 | +void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) | ||
| 340 | +{ | ||
| 341 | + DeviceState *dev; | ||
| 342 | + SysBusDevice *s; | ||
| 343 | + | ||
| 344 | + dev = qdev_create(NULL, "ecc"); | ||
| 345 | + qdev_set_prop_int(dev, "version", version); | ||
| 346 | + qdev_init(dev); | ||
| 347 | + s = sysbus_from_qdev(dev); | ||
| 348 | + sysbus_connect_irq(s, 0, irq); | ||
| 349 | + sysbus_mmio_map(s, 0, base); | ||
| 350 | + if (version == ECC_MCC) { // SS-600MP only | ||
| 351 | + sysbus_mmio_map(s, 1, base + 0x1000); | ||
| 352 | + } | ||
| 353 | +} | ||
| 354 | + | ||
| 355 | +static void ecc_register_devices(void) | ||
| 356 | +{ | ||
| 357 | + sysbus_register_dev("ecc", sizeof(ECCState), ecc_init1); | ||
| 358 | +} | ||
| 359 | + | ||
| 360 | +device_init(ecc_register_devices) |
hw/sun4m.h
| @@ -63,6 +63,6 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl); | @@ -63,6 +63,6 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl); | ||
| 63 | #include "sparc32_dma.h" | 63 | #include "sparc32_dma.h" |
| 64 | 64 | ||
| 65 | /* eccmemctl.c */ | 65 | /* eccmemctl.c */ |
| 66 | -void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version); | 66 | +void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version); |
| 67 | 67 | ||
| 68 | #endif | 68 | #endif |