gwj / at91sam9263 · Commits

Commit 475dc65f6d33d8f457d5731c38618b0b3d4e127c

Authored by aurel32
1 parent 8098ed41

PCI: Mask writes to RO bits in the command reg of PCI config space 

The Command register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.

Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6092 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 8 additions and 0 deletions
hw/pci.c
  View file @475dc65
... ... @@ -417,6 +417,9 @@ void pci_default_write_config(PCIDevice *d,
417 417 if (can_write) {
418 418 /* Mask out writes to reserved bits in registers */
419 419 switch (addr) {
  420 + case 0x05:
  421 + val &= ~PCI_COMMAND_RESERVED_MASK_HI;
  422 + break;
420 423 case 0x06:
421 424 val &= ~PCI_STATUS_RESERVED_MASK_LO;
422 425 break;
... ...
hw/pci.h
  View file @475dc65
... ... @@ -69,6 +69,11 @@ typedef struct PCIIORegion {
69 69  
70 70 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
71 71  
  72 +/* Bits in the PCI Command Register (PCI 2.3 spec) */
  73 +#define PCI_COMMAND_RESERVED 0xf800
  74 +
  75 +#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
  76 +
72 77 struct PCIDevice {
73 78 /* PCI config space */
74 79 uint8_t config[256];
... ...